The CPU input/ output instructions and resets operate in a manner identical to those specified in IBM 3250 Graphics Display System Component Description, GA33-3037; IBM System/ 3 70 Principles of Operation, GA22-2700; and OEM/
Channel-to-Control-Unit Inter[ ace, GA22-697 4.
The normal interaction between the controller and its host CPU is controlled by channel commands; these commands are conveyed to the controller by the Start I/O (SIO) or Start I/0 Fast Release (SIOF) instructions from the CPU. Several additional CPU instructions, including Test I/O, Halt I/O, Halt Device, and Clear I/ 0, also give the host program a means of access to the processor.
The controller responds to the Test I/O instruction, executed by the CPU, with a status byte. If there is no outstanding status information for the addressed device, an all-zeros status byte is returned. Status for any other device is not reset. Any status for the addressed device is reset at the end of the sequence.
Following an initial selection sequence issued to the controller, the current poll in progress is subjected to a controlled termination, except when the command is a Test I/O or a No-Operation, in which case the poll in progress is allowed to continue normally. In addition, if a poll is not in progress, a Test I/O or Na-Operation does not prevent initiation of the next poll cycle or prevent the presentation of data from a completed poll cycle. This allows pending interrupt conditions to be cleared by the Test I/O loop, although this is not recommended.
The poll in progress or the next poll issued is not necessarily to the device holding the interrupt condition, but, if sequential polling is allowed to continue, a poll is eventually issued to the required device and the interrupt condition is cleared from the device.
A Halt I/ 0 instruction may cause the channel to issue an interface disconnect sequence to the controller, resulting in the termination of the current I/ 0
operation. This does not affect display program processing currently in progress.
The interface disconnect sequence can be issued at various phases of interface activity, including during a data transfer. Any pending status is preserved and provided to the channel after the sequence has been completed.
Halt Device instruction processing is similar to Halt I/ 0 processing. Refer to IBM System/ 3 70 Principles of Operation, GA22-2700, for a description of the differences.
A System Reset causes the controller and all attached devices to be reset. A 5085, as a result of seeing the System Reset, effects a Selective Reset to each 5085 device. Any outstanding status or interrupts are lost. The diagnostics are not run following a System Reset. Also, the ready
I
not ready state of attached devices is not changed by a System Reset, but may be changed if the reset clears inhibiting conditions. If selected during the reset procedure, the controller responds with a status of Busy /Modifier during its reset procedure and automatically begins polling after the reset is complete. An asynchronous Control Unit End is generated at this time.Selective Reset
Status Information
Initial Selection Sequence
The Selective Reset resets the device that is in operation at the time Selective
Reset is detected. The reset clears attention pending status and sense, if any. In 1~ addition, the reset clears the link between the controller and processor and
ensures that the alphanumeric keyboard is enabled (if not the RS232C
Attachment Feature). Other devices on the same controller are not affected. If selected during the reset procedure, the controller responds with a status of Busy /Status Modifier and generates an asynchronous Control Unit End, if required, at the completion of reset processing.
The status indication is a byte of information sent from the controller to the channel:
• During the initial selection sequence At the ending phase of an operation
• When an asynchronous condition (for example, pick detect) occurs The status byte is reset after it has been accepted by the channel.
During the initial selection sequence a status byte is sent in response to a command. An all-zeros status is sent if the command is accepted, except for the following immediate control commands: Insert Cursor, Remove Cursor, and Set Audible Alarm, which return Channel End; and No-Operation, which returns Channel End and Device End status.
If a command is not accepted because of error conditions, the Unit Check bit alone is set in the status byte; that is, for invalid command codes, Bus-Out Check on the command byte, and Intervention Required conditions.
If the controller has status pending for the addressed processor, the response is a status byte containing the pending status; for any command except Test I/O, a Busy status bit is included and the command is not accepted.
If the controller has status pending for another workstation, the response is a Busy bit plus a Status Modifier bit (Control Unit Busy) and the command is not
accepted.
If a selection is issued to a device for which the controller has returned a Channel End, but Device End has not been generated, the response is either Busy, Status Modifier (Control Unit Busy), or Busy alone, depending on timing and the command in progress. The command is not accepted.
If the controller is selected during System Reset, Selective Reset, and interface disconnect processing (for example, Halt I/0), the response is Busy /Status Modifier set in the status byte (Control Unit Busy), in which case Control Unit End status is returned at the completion of reset processing.
' \
v
( I
~/
u
Ending Conditions
When a data transfer is involved in a command, the channel and the controller work together to perform the transfer. At the end of the operation the status for that operation is presented by the controller.
Two status conditions, Channel End and Device End, indicate the end of a channel operation. The Channel End status condition means that the device has finished with the channel facilities following a control or data transfer operation, if any. The Device End status condition indicates that the device has finished the operation and is ready to accept a new command. Device End can occur at the same time as Channel End or later. If command chaining is taking place, a new operation may be initiated following presentation of the Device End bit.
Disconnection from the channel will be signaled by the channel after Channel End, if block multiplexing is taking place.
Channel End is presented with initial status and Device End is presented at the completion of the following commands:
Insert Cursor
• Remove Cursor Set Audible Alarm
Separate Channel End and Device End status indications are generated and presented to the channel at the end of data transfer for the following commands:
Read Buffer
Read Cursor (if no cursor, or cursor not found) Read Memory Area
Select Read Memory Area
• Select Write Memory Area
• Set Buffer Address Register and Start Set Buffer Address Register and Stop
• Set LPFK Indicators Set Mode
• Write Buffer
• Write Memory Area
• Write Structured
Channel End is presented with Device End during initial status for:
• No-Operation
Channel End and Device End are presented together at completion for:
• Read Cursor (if cursor is found) Read Manual Input
Read X-Y Position Register Sense
• Sense ID
Unit Check may be returned either alone, with Device End, or with both Channel End and Device End, and resets the chaining condition if the condition existed.
lnte"upt Conditions
An asynchronous interrupt condition exists when the controller is not selected by the channel (for example, the host does not have a read outstanding), but the controller and/ or processor have generated or detected a condition that requires assistance from the host system. Interrupts may occur when any of the following occurs:
• Pick detect
Lighted program function keyboard (LPFK) action
• Simulated LPFK action, ENTER key, or Cancel key from the Begin Order Processing ( GBGOP) order
• Store Device Input ( GSDEVI) order interrupt
• ENTER, Cancel, or program function key from the alphanumeric keyboard (ANK)
End Order Processing (GEOP) order
Uncorrectable memory error (see Note below) Asynchronous Device End
• Unsolicited Attention, Device End, Unit Exception status indications (the processor becomes ready; for example, by being switched on)
Asynchronous status after a Halt I/ 0 instruction
• Asynchronous Control Unit End status indication Errors encountered during display program processing
The controller initiates a sequence to gain selection on the channel. When selection is achieved, the controller sends a status byte containing the appropriate bits, depending on the condition causing the interrupt. The status may also be retrieved by a Test 1/0 instruction or Start 1/0 instruction.
When a GBGOP order simulates (via Set Manual Input) an LPFK, ENTER or Cancel keystroke, an Attention interrupt is generated.
Unsolicited Attention/Device End/Unit Exception status indications are generated by the controller when a not-ready device becomes ready.
Note: If an uncorrectable memory error occurs in a processor display storage at a time when no channel command to that processor is in progress, all graphic order processing within the processor stops and an Attention/ Unit Check interrupt is generated, with Memory Error set in the sense byte (the Unit Specify bit is set to zero to indicate an error in the processor). Restart/retry of any operations that were in progress vary with the application.
\.
.
....,,)(
\_J