Graphics Processor Architecture

Display Storage

Frame Buffers

The IBM 5085 Graphics Processor contains either one or three physical display storage areas, depending on whether the RS232C Attachment Feature is

included. Channel I/ 0 commands direct data to the appropriate display storage according to the device address.

The first, or graphics, display storage is associated with the 5081 Display and consists of a minimum of 3 2K bytes of random access memory (RAM). This storage is used to hold the display program and data that control activity at the 5080 Graphics System workstation. Although the 5085 comes with a 56K-byte display storage area, the user may reduce the size of this area to 32K bytes through the use of memory area definitions.

• Two additional display storage areas are associated with the RS232C

Attachment Feature and consist of 16K bytes of RAM each. These are used to hold programs and data that control the RS232C ports. Refer to Chapter 6 for details.

The display storage area associated with the 5081 Display contains pages of 64K (65,536) bytes. The last page may range from 2K bytes to 64K bytes, but, if only one page exists, it must never be less than 32K bytes. A Branch Page (GBPAGE) order and a Branch after Push Link (GBAPL) order are provided to transfer control between pages. The result of any attempt to cross the display storage page boundary without using these orders is unpredictable. The pages are numbered from zero upward. Programs can reference pages other than zero only by using the Write Structured and memory area channel commands and the GBP AGE and GBAPL orders.

Each pair of display storage bytes, beginning with bytes 0 and 1, forms a display storage word. Graphic orders are aligned on word boundaries, and each order occupies an integral number of words. Graphic and alphanumeric data fields are word-aligned, each field occupying one or more words.

The display storage must contain a display program in order for the graphics system workstation to become active. This program controls the display of graphic and alphanumeric data on the display, as well as the actiOJ.1 taken upon detection by the pick device of a line, marker, character, and so on, within the displayed image. The display program also coordinates the generation of interrupts due to keyboard action at the workstation and at other input devices, such as the dials feature.

The processor is a raster device that employs frame buffers to hold the image that is ultimately displayed on the display. As the processor interprets the display program in display storage, the image data produced by such functions as

line-to-raster conversion, character generation, and so on, is stored into the frame buffer. The stored data is scanned and converted to video signals and passed to the display.

Each frame buffer is 1024 x 1024 pixels (bits) and may be up to eight planes in depth. The processor provides options of 2-, 4-, 6-, and 8-bit planes. The number of bit planes controls the number of colors or grayshades that you may simultaneously display.

The bit planes are numbered as follows:

High Order Low Order

0 1 2 3 4 5 6 7

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2 bit planes 4 bit planes

6 bit planes 8 bit planes

If a processor has less than eight bit planes, the high-order bits are discarded and the remaining bits are loaded according to the diagram above.

To avoid flashing on the display screen (due to dynamic image updating and graphic monitor refresh memory contention), the processor is equipped with a double buffer. This provides two sets of frame buffers and enables preparation of a new image in one frame buff er while the other frame buffer is used for

refreshing the image being displayed. After preparing the new image, the buffers are switched. The buff er having the new image is used to refresh the display

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image, and the one having the old image is used for preparing the next new image. :, , 'l The frame buffers are switched at vertical retrace time in order to keep the image ~

from breaking up.

The frame buffers are switchable and erasable under display program control.

(See "GBGOP-Begin Order Processing" on page 5-8.) Display Storage Page Numbering

The graphics processor supports a maximum of 17 pages; accordingly, valid page number values are in the range X'OOOO' to X'OOlO'. However, the number of pages supported by your processor may be less, depending on the amount of storage installed, and may vary from time to time, depending on whether a memory area storage pool exists and, if it does, how large it is.

You may calculate the number of pages available at any time in your processor, and, by doing so, the valid page number values, by issuing a Store Configuration Data (GSCONF) order and reading back the configuration data stored in display storage. Then, from parameter 2 (graphics system storage size) extract the number of 2K blocks of storage assigned to display storage. Divide this number by 32; the quotient gives you the number of full 64K pages available for display storage use and the remainder, if not zero, indicates that you have an additional (last) page of 2K to 64K. (See "Memory Areas" on page 2-6 for details.) An attempt to branch to an invalid page results in a display program error.

Contact your system programmer for details on page numbers available to your application.

Display Programs

A display program, which consists of graphic orders interleaved with data, is contained in one or more areas within display storage.

The graphic orders and data that form a display program are assembled by software in the host CPU. The host CPU software also transmits the display program to the display storage and initiates execution of the display program using the commands described in "Graphics Channel Controller Commands" on page 2-2.

Each display program must contain either a Begin Order Processing ( GBGOP) or Start Regeneration Timer (GSRT) order. If a display program executes for 30 seconds without encountering either a GBGOP or GSRT order, program execution is terminated and an Attention/Unit Check interrupt is presented to the host system.

Management of display storage is a user function for which host software

conventions or controls are required. The display storage can contain orders and data not in the flow of control of currently executing display programs.

After the host has initiated the execution of a display program (with a Set Buffer Address Register and Start command or a Start Display Program structured field), execution proceeds continuously until terminated either by the host, a pick detect interrupt, an End Order Processing ( GEOP) order or other similar condition (see

"Display Program Termination" on page 3-10).

If the switch buffer mode is invoked by a GBGOP order (with d=O), or a GSRT order (by default), the frame buffers are switched during execution of the

GBGOP or GSRT order. The frame just executed (and rastered) is displayed, and the next frame is rastered into the alternate frame buffer. Frame buffer switching is synchronized with video refreshing; the display program processor does not complete execution of the GBGOP or GSR T order until frame buff er switching and clearing are complete. During the clearing operation, only those frame buffer bit planes with the corresponding write protect mask bits set to zero are cleared.

If the nonswitch frame buffer mode is on (GBGOP order, with d=l), the frame buffers are not switched or cleared.

Notes:

1. A GBGOP or GSRT order should begin each display program to ensure the appropriate states are set and that the frame buffer is cleared. However, display programs that do not begin with a GBGOP or GSR T order will execute.

2. A GBGOP or GSR T order must be issued to cause an image to be displayed on the display screen. Execution of a GEOP order does not result in switching the frame buffers. Therefore, a simple program starting with a GBGOP or GSRT order and ending with a GEOP order will not result in the displaying of an image.

Display Program Processor

3. Due to the speed of the host link, it may be possible to load, start, and stop a display program before image generation and frame buffer switching can take place. Accordingly, the user should use a timer in any host application that

would behave in such an unsolicited mode, to ensure that the image is \~

displayed.

The following registers and table are maintained by the display program processor to control execution of the display program:

Display storage address register Regeneration address register

• Attribute registers Stack registers

Cursor address register X-Y-Z position registers Condition code register Color Table

Display Storage Address Register (DSAR)

The display storage address register, which contains a page number and an address within that page, controls display storage access during certain channel commands.

The contents of the display storage address register may be changed by:

Execution of a Write Structured command containing a Stop Display Program or Set Display Storage Address Register structured field issued by the host system.

In the context of 3250 compatibility, the DSAR and buffer address register (BAR) of the 3250 are equivalent. Accordingly, the contents of the DSAR are also changed by the following 3250-compatible commands:

A Set Buffer Address Register and Stop command issued by the host system.

The page number is set to zero.

A Set Buffer Address Register and Start command issued by the host system (also sets the regeneration address register). The page number is set to zero.

• Execution of a Write Buffer command issued by the host system.

Execution of a Read Buff er or Read Cursor command issued by the host system.

The display storage address register is set to zero at power-on or system reset, that is, address zero of page zero.

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Notes:

1. During Read Buffer, Read Cursor or Write Buffer commands, the display storage address register is incremented to address each word sequentially in the buffer.

2. During Select Write Memory Area, Select Read Memory Area, Write Memory Area, and Read Memory Area channel commands, the display storage address register is not changed. In addition, the memory area control structured fields have no effect on this register.

Regeneration Address Register (RAR)

Attribute Registers

Stack Registers

Cursor Address Register (CAR)

The regeneration address register, which contains a page number and an address within that page, controls the processing of instructions in the display program.

The contents of the regeneration address register may be changed by:

Normal display program processing.

A Write Structured command containing a Start Display Program structured field (at the next GBGOP or GSRT order if the display program is running).

A Set Buff er Address Register and Start command issued by the host system (the DSAR is copied into the RAR). The page number is set to zero.

The regeneration address register is set to zero at power-on or system reset, that is, address zero on page zero.

Attribute registers contain the current values of blink, line type, marker, image plane control, highlight control, color

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grayshade attributes, pick controls, and so on. Attribute registers may be changed during execution of a display program to assign different attributes to components of the image.

For further details on these registers, their control and default settings, see

"Attribute Control Orders" on page 5-31.

Stack registers contain the stack size, location, and stack current pointer. Stack registers may be changed during execution of a display program.

For further details on stack registers, their control and default settings, see "Stack Control Orders" on page 5-57.

The cursor address register contains the display storage address and page number of the character mode data field to which the cursor is assigned. Entering an alphanumeric character places the character code into the addressed data field and, normally, moves the cursor to the next character location in the data list. For further details, see "GDCHAR-Draw Character" on page 5-24 and "ANK Input and the Cursor" on page 3-12.

X-Y-Z Position Registers

The contents of the cursor address register are also updated by the host system with an Insert Cursor or Remove Cursor command or a Set Cursor Address or Reset Cursor Address structured field.

The cursor address register is set to zero at power-on or system reset.

X-Y-Z position registers show the coordinates of the currently addressed point, or current draw position (CDP), in world coordinate space. They are maintained as signed 16-bit pretransformation world coordinate values in the range of -32K to

+32K. Negative values are maintained in twos complement form. (See

"Coordinate System Specification" on page 3-27 .)

The contents of the X-Y-Z position registers may be interrogated by the host system by issuing a Sense command. Bytes 14-19 of the sense data contain the X-Y-Z values of the X-Y-Z position registers. If the Sense command is issued in response to a pick deteCt (see "Pick Control" on page 3-19), the X-Y-Z values should be interpreted as follows:

In graphics mode the X-Y-Z values represent the coordinates of the current draw position.

• In character mode, if the character set ID ( CSID) in attribute register 18 is X'OO', the X-Y-Z values represent the center point of the character following the character upon which the detect occurred.

In character mode, if the CSID is not X'OO', the X-Y-Z values represent the lower left corner point of the character following the character upon which the detect occurred.

• If the Sense command is issued and the pick interrupt was the result of a Store Device Input (GSDEVI) order causing byte 1, bit 6 of the sense data to be set, the value of the X-Y-Z coordinates returned represents the current tablet (stylus or cursor) position. The Z value is set to zero.

If the Sense command is not sent in response to a pick detection interrupt, the value of the X-Y-Z (current draw) position registers is returned, but the

significance of the value depends on the display program and the point at which it was last stopped.

The Store Device Input (GSDEVI) order may also be used to access the X-Y-Z position registers from a display program.

The contents of the X-Y-Z position registers may also be interrogated (in

3250-compatibility mode) by issuing a Read X-Y Position Register command or a Store X-Y Position Registers ( GSXY) order. In this case, the Z value is ignored and the four high-order bits of the X and Y values are set to zero.

The X-Y-Z position registers are set to zero at power-on or system reset.

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Condition Code Register

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The Z value is maintained even if the Transformation and Clipping Feature (TCP) is not installed or is installed and 3D mode is not active. ^If output primitive (graphic) orders are ^not used that specify a Z coordinate, the Z register remains zero. If orders specifying a Z coordinate are used, the Z register is updated accordingly. In those cases where the TCP is not installed or 3D mode is not active, the Z coordinate and/ or the Z register is ignored during vector-to-raster (line-to-raster) conversion.

A 2-bit condition code register is provided to retain certain conditions that may occur while processing display programs. The contents of this register can be tested by the Branch on Condition ( GBC) order (see "Branch Control Orders"

on page 5-53 for details).

The condition code register is set under the following conditions:

Setting

Condition 00 01 10 11

GSRT PI off and PI off and Not set Not set

GBDD TSI off TSion

GBND GBGSEG SBA Start WS Start

GEAF PI off and PI off and PI on and PI on and

GESEG TSI off TSion TSI off TSion

GLATR GDPXL GD CIR GB GOP

GADD Sum=O Sum< 0 Sum> 0 Overflow

GSUB Diff. = 0 Diff. < 0 Diff. > 0 Overflow

GCOMP Equal 1st oper 1st oper Not set

low high

GMUL 16-bit 32-bit Not set Not set

product product

GDIV No Overflow Not set Not set

GSHIFT overflow

GSDEVI All switches AU switches Out of Device not

off for on for presence installed

referenced referenced device device

GTM All Os Mixed Os and ls Not set ^{All ls} Notes:

1. See "Pick Detection Modes and Indicators" on page 3-20.

2. For a more complete description of the condition code settings, see the individual order descriptions.

Color Table (CT)

Default Color Table

3. The RS232C Attachment Feature has separate condition code registers (see

"RS232C Port Condition Codes" on page 6-5 for details).

None of the remaining orders affect the condition code setting; it is preserved until changed by one of the above conditions.

The Color Table (CT) controls the grayshade level on 5081 monochromatic models and the color on 5081 color models.

The Color Table is loaded by the Load Color Table ( GLCT) order executed by the display processor, and allows flexibility to choose the colors or grayshade levels that are used concurrently from a larger number of potential colors or grayshades.

The Color Table contains 256 locations for color or for monochrome. Each location is 12 bits wide.

In a monochromatic model, all 12 bits control the grayshade level. In a color model, the 4 high-order bits control the intensity of the blue, the next 4 bits control the intensity of the green, and the low-order 4 bits control the intensity of the red.

On a color system there is a choice from a range of 4096 possible colors, up to 256 of which can be active at one time, depending on the number of planes in the frame buffer. A monochrome system supports the simultaneous display of up to 256 grayshades, depending on the number of planes in the frame buffer.

In summary, the Color Table provides a means of translating the output of the bit ¹_~ planes in the frame buffer to actual colors/ grayshades on the display.

Figure 3-1 on page 3-9 illustrates the format and use of the Color Table and its relationship to the frame buff er bit planes.

At system initialization time the Color Table is loaded with default values.

The first eight entries (0-7) simulate 3250-compatible intensity levels, providing varying shades of gray increasing in intensity from entry 1 to entry 6. Entry 0 specifies black and entry 7 specifies white. The entries are:

Entry Number

For 2-bit planes, value is X'BBB' For 2-bit planes, value is X'CCC' For 2-bit planes, value is X'FFF'

The remaining entries are loaded with various color

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grayshade values to ensure a display if the entry is referenced.

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Notes:

1. The same values are loaded whether the 5081 is a color or monochrome model.

2. Color Table entries 3, 15, 63, and 255 are loaded with a value of X'FFF' to generate a white color

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grayshade. These entries constitute the logical end of the Color Table for systems with 2-, 4-, 6-, or 8-bit planes.

Monochromatic - - - 1 2 bi t s

-1

_Posn

Index

I

- Value

Frame MSB

I

Buffer -

1

Color/Grayshade Control

Color ¹² bits

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I I ^Posn

Index

1

Value

Frame MSB

Buffer

I I ^{Blue Green Red}

Figure 3-1. Color Table Use and Structure

Display Program Initiation

A display program is started upon:

Receipt from the host of a Write Structured command containing a Start Display Program structured field (code X'27'). The program is started at the storage address currently set in the display storage address register. If the display program is already running, it continues until it encounters a GBGOP or GSR T order; then it is immediately restarted.

• Receipt of a Set Buffer Address Register and Start command from the host CPU. The program is started at the new display storage address contained in the command. If the display program is already running, it is immediately terminated and restarted.

Display Program Termination

A display program is terminated by any of the following events:

1. The program is asynchronously terminated upon:

Receipt from the host CPU of a Write Structured command containing a Stop Display Program structured field (code X'07').

Receipt of a Set Buffer Address Register and Stop command from the

Receipt of a Set Buffer Address Register and Stop command from the

Im Dokument '-Graphics System (Seite 42-53)