If a 5085 hardware error occurs during the read operation, the command is terminated with Device End and Unit Check bits set in the status byte, and Hardware Error (byte 1, bit 4) and Memory Error (byte 5, bit 0) set in the sense
byte.
\..._,-A Read Memory Area command chained from a Select Read Memory Area command returns a Channel End status indication at the end of data transfer, followed by a separate Device End status indication.
The Select Read Memory Area command transfers a block of data from a processor memory area to the controller. The memory area is identified by a name (identifier). The identifier of the memory area, 2 flag bytes, address of the data block to be transmitted (that is, data block offset), and the size of the data block are defined in a 10-byte field transmitted from the System/370 channel.
The format of these 10 bytes is:
Bytes 0-1
Memory area type-dependent flags
Bit 0 Read to the cursor indicator for type X'02' Bit 1 Read cursor address indicator for type X'02' Bits 2-7 Reserved
Data block off set Data block count
Memory Area Identifier: The memory area identifier (bytes 0 and 1) specifies a predefined memory area (see "Memory Areas" on page 2-6).
Common Flags: The functions defined for the common flags (byte 2) apply in the same manner to all memory area types.
Bit 0 of the common flag byte is the validity bit. If this bit is zero, bytes 4 through 7 contain a valid data block off set. If this bit is 1, the contents of bytes 4 through 7 are ignored and the current transfer address is used to define the start of the data block to be transmitted.
If the memory area identifier is X'FFFF', these flags are ignored.
·Memory Area Type-Dependent Flags: The functions defined for the memory area type-dependent flag (byte 3) depend on the type of the addressed memory area.
The meaning of bits 0 and 1 when the memory area type is X'02' (display storage) is:
• Bit 0 = 1 : The transfer of data from display storage to the controller is terminated when either the number of the data bytes transferred is equal to the value of the count field or a display storage location to which the cursor is assigned is enconntered.
Bit 0 = 0: The transfer of data from display storage to the controller is terminated when the number of the data bytes transferred is equal to the value of the count field.
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Bit 1
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1: A 4-byte offset of the cursor is transferred to the controller. The values of bit 0 of byte 2, bit 0 of byte 3, and bytes 4 through 7 are ignored.• Bit 1
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0: Normal Select Read Memory Area command operation.Data Block Of /set: Data block offset (bytes 4 through 7) is a 4-byte field that specifies the address of the first byte of the data block to be transmitted. This is not an absolute processor memory address; it is the relative address of the first byte of the data block with respect to the beginning of the memory area. Data block offset values range from 0 through n, where n is the number of 2K blocks assigned to the specified memory area times (x) 2048 bytes minus 1. If the validity bit is zero, the data block offset is added to the starting address of the memory area by the processor to generate the current transfer address (see
"Memory Area Control Table" on page 2-11). The value of the current transfer address in the Memory Area Control Table is not replaced by the contents of the data block offset field if the validity bit is 1.
Data Block Count: The data block count field (bytes 8 and 9) contains the length, in bytes, of the data block to be transmitted. The maximum allowable value is 32,768.
When the processor receives a Select Read Memory Area command, the data is sent to the controller. The value of the current transfer address in the Memory Area Control Table is incremented as data is read from the memory area. The controller stores the data. It does not send it across the channel to the host system until the data is fetched from the controller to the CPU by a chained Read Memory Area command. If no command is chained or the chained command is not a Read Memory Area command, the data stored in the controller is not retained.
The length of the data transmitted to the controller in response to a Select Read Memory Area command is determined by the data count passed by that
command. The data transmitted across the interface in response to a subsequent chained Read Memory Area command is the smaller of the channel control word (CCW) count fields in that Read Memory Area command and the data count passed by the preceding Select Read Memory Area command. Incorrect length (generated by the channel if the SLI bit is off) is returned with the chained Read Memory Area command if the preceding Select Read Memory Area command passed a different count value. A Read Memory Area command chained to a Select Read Memory Area command returns a Channel End status indication at the end of data transfer, followed by a separate Device End.
If the Select Read Memory Area command count is greater than the channel Read Memory Area command count, the excess data is not held in the controller after the end of the Read Memory Area command. In other words, it is not possible to command-chain multiple Read Memory Area commands to pick up data from a single Select Read Memory Area command.
Note: Data chaining may be used to transfer data betweell: the System/370 CPU and the channel, as data chaining is a channel function and not a control unit (controller) function.
Channel End and Device End status indications are returned separately for the Select Read Memory Area command. Channel End is presented when the command and the count value are accepted by the controller. Device End is presented when the requested data is stored in the controller and the dialogue between the controller and the processor is complete.
The following exception conditions cause Device End and Unit Check to be presented. Sense byte 1, bit 7 (Program Error) is set to 1. The exception conditions are:
• The addressed memory area does not exist; that is, the memory area has not been defined previously by a Define Memory Area or Rename Memory Area structured field and is neither memory area X'FFFF' nor X'FFFE'.
• The data block off set is larger than the size of the addressed memory area or the data block off set plus the data block count exceeds the size of the memory area (that is, wrap would have occurred). If the latter is true, sense byte 4, bit 6 (Invalid Memory Area Address) is also set on. The current location is not changed.
The following exception condition causes Device End and Unit Check to be presented and sense byte 0, bit 0 (Command Reject) to be set to 1.
• Length of the data associated with the command is less than 10.
If the processor is busy processing the data for more than the device working timeout period (about 3 seconds), Device End and Unit Check are presented and Device Working Timeout (sense byte 4, bit 1) is set.
Any Unit Check status error causes chaining to be broken. The integrity of the data in the controller is not guaranteed under these circumstances.
If a hardware error occurs during a read operation, the Select Read Memory Area command is terminated with Device End and Unit Check bits set in the status byte and Hardware Error (byte l, bit 4) and Memory Error (byte 5, bit 0) set in the sense bytes.
Notes:
1. A Read Memory Area command chained to a Select Read Memory Area command addressing memory area X'FFFF' can be used by the application program to obtain the hexadecimal image of a segment of, or the entire, Memory Area Control Table.
2. If the value of the data block count field exceeds 32, 768 bytes, the Select Read Memory Area command is rejected with Device End and Unit Check status indications; and Command Reject (sense byte 0, bit 0) is set.
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Select Write Memory Area
The Select Write Memory Area command selects a processor memory area for subsequent write operations. The name of the memory area (memory area identifier), a flag byte, the address of a location within the named memory area from which the writing is to start, and the size of the data to be written are transmitted from the channel in a 10-byte field in the following format:
Bytes 0-1 Byte 2
Byte 3 Bytes 4-7 Bytes 8-9
Memory area identifier Common flags
Bit 0 Data block off set validity Bits 1-7 Reserved
Reserved
Data block off set Data block count
Memory Area Identifier: The memory area identifier (bytes 0 and 1) specifies a predefined memory area (see "Memory Areas" on_ page 2-6).
Common Flags: The functions defined for the common flags (byte 2) apply in the same manner to all memory area types.
Bit 0 of the common flag byte is the validity bit. If this bit is zero, bytes 4 through 7 contain a valid data block off set. If this bit is 1, the contents of bytes 4 through 7 are ignored and the current transfer address is used to define the address where the first byte of the data block to be transmitted is to be stored.
Data Block Of /set: Data block offset (bytes 4 through 7) is a 4-byte field that specifies the address of where the first byte of the data block to be transmitted is to be stored. This is not an absolute memory address; it is the relative address of the first byte of the data block with respect to the beginning of the memory area.
Data block offset values range from 0 through n, where n is the number of 2K blocks assigned to the specified memory area times (x) 2048 bytes minus 1. If the validity bit is zero, the data block offset is added to the memory area starting address contained in the Memory Area Control Table to generate the current transfer address (see "Memory Area Control Table" on page 2-11). If the validity bit is 1, the value of the current transfer address in the Memory Area Control Table is not changed.
Data Block Count: The data block count field (bytes 8 and 9) contains the length, in bytes, of the data block to be transmitted. The maximum allowable value is 65,536.
The Select Write Memory Area command initializes the current transfer address of the memory area.
Channel End and Device End status indications are returned separately for the Select Write Memory Area command.
Sense
Determining X-Y-Z Position
An exception condition causes Device End and Unit Check to be presented; the current transfer address is not changed. Sense byte 1, bit 7 (Program Error) is set to 1. The exception conditions are:
• The addressed memory area does not exist; that is, the memory area has not been defined previously by a Define Memory Area or Rename Memory Area structured field and is neither memory area X'FFFF' nor X'FFFE'.
• The addressed memory area is a read-only memory area.
The data block off set is larger than the size of the addressed memory area or the data block offset plus the data block count exceeds the size of the memory area (that is, wrap would have occurred). If the latter is true, sense byte 4, bit 6 (Invalid Memory Area Address) is also set on. The current location is not changed.
The following exception condition causes Device End and Unit Check status bits ....
to be presented and sense byte 0, bit 0 (Command Reject) to be set to 1.
Length of the data associated with the command is less than 10.
If the processor is busy processing the data for more than the device working timeout period (about 3 seconds), Device End and Unit Check status bits are presented and sense byte 4, bit 1 (Device Working Timeout) is set.
Any Unit Check status error causes chaining to be broken.
' The Sense command obtains data relative to the status of the addressed device. It
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can be issued by the host system at any time, but is usually the response to a Unit Check status. When a Sense command is issued at any other time and status is pending for another device on the controller, the controller responds with Busy and Status Modifier at initial selection.
The amount of sense data returned depends on the type of device, controller, and mode setting (see "Sense Information" on page 4-29). The error indicator portions of the sense data are reset following successful completion of this command. Additional· conditions for the resetting of sense data are defined in
"Sense Information."
Selections to other devices are allowed while one or more devices are in a Sense command pending state, because the controller maintains the sense data individually by device.
The Sense command provides Channel End and Device End together.
The host system, when communicating with a 5085 Graphics Processor attached to a 5088 Graphics Channel Controller, may retrieve the X-Y-Z position registers associated with the display by issuing a Sense channel command in response to a pick detect or at any other time. See "X-Y-Z Position Registers" on page 3-6 and Appendix C for details.
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