Advanced Digital Testing using HDLs
5.4 Proposed ATPG Approach using Fault In- In-jection Testing
5.4.2 Proposed ATPG and Experimental Set-up
The proposed simulation-based test approach consists of different components and shown in Figure 5.8267. The top-level file consists of the golden model–fault free design–instantiations, faulty models (generated by the RASP-FIT tool) instantiations, comparator block (compare the responses), dynamic compaction block, and memory (to store responses in a text file). The top file code, along with the various components, is also generated by the RASP-FIT tool during the FIA process. The essential blocks are described in the sequel.
265Fault Injection Selection Activation
266 [JG03] Jha and Gupta. Testing of Digital Systems. 2003
267 [KHB16a] Khatri, Hayek, and Börcsök. Applied Reconfigurable Computing. 2016
Figure 5.8: Test approach with the simulation environment.
Input Pattern Generator
This block is used to generate different input patterns which are simultaneously applied to both the original and faulty copies of the SUT. For small circuits having few input ports, we generate and apply all possible combination of inputs.
For a large number of inputs, random input patterns are generated and applied to the golden module and faulty modules simultaneously. These patterns are generated using the Linear Feedback Shift Register (LFSR), defined in the test-bench. Figure 5.9 shows the code for the generation of input patterns randomly for the SUT (c432.v) having 36 inputs.
// Random input generator code f o r 36 input design reg [ 3 5 : 0 ] e = 36 ' hF59611d09 ; // seed
always @( c l k ) begin
e = { e [ 3 4 : 0 ] , e [ 3 5 ] ^ e [ 3 4 ] } ; {N1 , N4 , N8 , N11 , . . . , N73 , N76} = e ; end
Figure 5.9: Generate random input patterns in test-bench.
To generate a seed value randomly, a program in Matlab is written, which takes the number of inputs of SUT and generates the hexadecimal number.
In this example, the number of inputs of SUT is 36, and it generates the
‘F59611d09’ as a seed. The users can generate as many seeds as they want.
Golden & Faulty Module
The good circuit or golden circuit is a fault-free version of the system under test.
It is a significant part of the testing tool. It generates the correct responses which are further compared to the responses of a faulty circuit under test.
As described earlier, the test method requires the introduction of faults in the target system deliberately268. FPGA designs are written in hardware description languages, mainly VHDL and Verilog HDL. Verilog designs are considered in the research, and the developed tool is designed specifically for Verilog. It injects fault in the design and generates the faulty module. Figure 5.2 represents the fault-free design and its Verilog representation is shown in Figure 5.10.
To be able to predict the behaviour of a defective system, or generate tests to find the defective parts, or in general, for any computer analysis of defects, a good fault model is needed. A good fault model is one that has a close correspondence with the actual defects, it is easy to represent in a computer program, and it is as brief as possible for an optimized computer processing time. In fault injection testing procedure, it requires a faulty module which runs in parallel with the golden module. Three fault models are used in this work, i.e. bit-flip, stuck-at 0 and stuck-at 1. Figure 5.10 shows the faulty module of the design with the bit-flip fault model and fault injection control unit. Faulty locations are shown in Figure 5.3.
Comparator Logic
This block compares the responses of the golden circuit with the responses of each faulty copy. The number of output pins of the comparator blocks depends on the number of faulty copies. The user can select any number of copies for moderate and large size circuits. The minimum numbers of copies are three.
A different number of copies would change the fault select lines and speed up the process. When the output of the comparator is logic ’1’, it means that the activated fault is detected, and when the comparator output is logic ’0’, it means the fault is not detected. The code for the comparator logic as an
268 [Nav10] Navabi. Digital System Test and Testable Design Using HDL Models and Architectures. 2010
// V er i l o g module
module c17 (N1 , N2 , N3 , N6 , N7 , N22 , N23) ;
input N1 , N2 , N3 , N6 , N7 ; output N22 , N23 ;
wire N10 , N11 , N16 , N19 ; nand NAND1(N10 , N1 , N3) ; nand NAND2(N11 , N3 , N6) ; nand NAND3(N16 , N2 , N11) ; nand NAND4(N19 , N11 , N7) ; nand NAND5(N22 , N10 , N16) ; nand NAND6(N23 , N16 , N19) ; endmodule
// Ver i l o g f a u l t y module
module c17_1 ( s e l e c t , N1 , N2 , N3 , N6 , N7 , N22_f1 , N23_f1 ) ;
input N1 , N2 , N3 , N6 , N7 ; output N22_f1 , N23_f1 ; wire N10 , N11 , N16 , N19 ; input[ 3 : 0 ] s e l e c t ; wire f i s =1;
reg f0 , f1 , f2 , f3 , f4 , f5 , f6 , f7 , f8 , f9 , f10 , f11 ;
always @ ( s e l e c t ) begin i f ( s e l e c t == 4 ' d0 ) begin f 0=f i s ; f 1 =0; f 2 =0; f 3 =0; f 4 =0; f 5
=0; f 6 =0; f 7 =0; f 8 =0; f 9 =0; f10
=0; f11 =0;end ..
.
e l s e begin
f 0 =0; f 1 =0; f 2 =0; f 3 =0; f 4 =0; f 5 =0;
f 6 =0; f 7 =0; f 8 =0; f 9 =0; f10 =0;
f11 =0;end end
nand NAND1(N10 , f 0 ^N1 , f 1 ^N3) ; nand NAND2(N11 , f 2 ^N3 , f 3 ^N6) ; nand NAND3(N16 , f 4 ^N2 , f 5 ^N11) ; nand NAND4(N19 , f 6 ^N11 , f 7 ^N7) ; nand NAND5( N22_f1 , f 8 ^N10 , f 9 ^
N16) ;
nand NAND6( N23_f1 , f10 ^N16 , f11 ^ N19) ;
endmodule
Figure 5.10: Verilog module and Verilog faulty module using RASP-FIT tool.
// Ver i l o g Code f o r Comparator Logic
always @ ( N1 or N2 or N3 or N6 or N7 or s e l e c t ) begin
cmp1 = (N22 ^ N22_f1 ) | (N23 ^ N23_f1 ) ;// 1 s t copy cmp2 = (N22 ^ N22_f2 ) | (N23 ^ N23_f2 ) ;// 2nd copy
.
cmpN = (N22 ^ N22_fN) | (N23 ^ N23_fN) ;. // Nth copy end
Figure 5.11: Verilog code for the comparator logic.
example given in Figure 5.10 by the developed RASP-FIT tool is shown in Figure 5.11.
Proposed Dynamic Compaction Scheme
The dynamic compaction is part of an ATPG process. Dynamic compaction is applied to the array, and the qualified test vectors Tq are obtained first and then theseTq are used for hardness analysis and static compaction. As dynamic compaction is part of the ATPG approach, therefore the Verilog code is added to the top-level file for this dynamic compaction by the RASP-FIT tool. It is a simple proposed approach and is given in Algorithm 1. The set-point value is a number which is the mean of outliers–observation points that are distant from other observations in the majority–obtained during fault injection experiments.
More details about the procedure to find the set-point values can be found in269. The steps of the dynamic compaction algorithm are given in Algorithm 1.
Algorithm 1 Dynamic compaction algorithm in a nutshell
1: Input patterns are applied using LFSR from total vector space TS
2: Fault detections are counted for each pattern applied
3: Sum of detections are compared with set-point value
4: if Is sum greater than or equal to set-point value then
5: Stored pattern as qualified test vectors Tq
6: Increment the number of Tq count
7: else
8: Apply new pattern to the SUT
9: end if
10: Go to step 2
11: Stop simulation when Tq count reaches 100
Memory Block
The memory block consists of rows and columns. The number of rows depends on the pattern applied, and the number of columns depends on the total number of faults injected and the number of inputs of the SUT. In this block, the qualified input test patterns from the dynamic compaction step are stored along with the array of faults. The resulting data are transmitted to the result analyser for the static compaction.
269 [KHB17] Khatri, Hayek, and Börcsök. “Validation of selecting SP-values for fault models under proposed RASP-FIT tool”. 2017