Introduction

FPGA has been involved in numerous applications in the last couple of decades because of many features as mentioned before in Chapter 1¹⁵⁷. Due to technol-ogy scaling, SRAM-based FPGA designs are susceptible to SEE which can be caused by many sources¹⁵⁸,¹⁵⁹,¹⁶⁰. It is also difficult to ensure an acceptable degree of reliability due to soft-errors. Therefore, it is essential to test and verify the designs. Both testing and verification require a deliberate introduction of faults in the SUT, which is called the fault injection technique.

Fault injection technique plays a vital role in testing and dependability analysis of target systems. In this technique, a fault is intentionally introduced into the SUT. The response of the fault-free system is compared with the copy of the SUT containing internal faults (faulty-system). After that, results are used in quantifying the verification and robustness of the SUT. Generally, FI techniques are separated into four: namely hardware, software, simulation, and emulation-based. Chapter 2 describes the various fault injection techniques and tools along with their advantages and disadvantages in detail. Notably, for FPGA-based systems, emulation and simulation-based techniques are suggested for fault injection testing, dependability analysis and fault simulation/emulation applications¹⁶¹.

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158 [Xin10] Xin. “Partitioning Triple Modular Redundancy for Single Event Upset Mitigation in FPGA”. 2010

159 [DSC14] Desogus, Sterpone, and Codinachs. “Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs”. 2014

160 [BK18] Benites and Kastensmidt. “Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuits”. 2018

161 [KHB18c] Khatri, Hayek, and Börcsök. “Validation of the Proposed Fault Injection, Test and Hardness Analysis for Combinational Data-flow Verilog HDL Designs under the RASP-FIT Tool”. 2018

Fault injection technique is adopted in the process of evaluation of fault effects and fault tolerance¹⁶². The fault injection technique consists of the deliberate insertion of faults into the particular target system and, monitors the responses to examine the effects of the faults. In a nutshell, the fault injection technique provides:

• The ability of a system to detect, locate, and recover from errors.

• The statistical estimation of soft-errors for dependability analysis.

• The evaluation of design characteristics for reliability.

• The measurement of the effectiveness of the fault tolerance capability of the design.

• The ability to find the critical components of an overall design.

• The way to test the digital design and obtains the test vectors for auto-matic test equipment.

• The way to calculate the fault coverage and code coverage for the design in the verification process.

There are various reasons for involving FPGA in developing of fault injection techniques and tools, such as prototype availability of designs (for simulation), fast emulation (also the high speed of injections), more on-chip area availability and (full & partial) reconfiguration techniques. The primary problem in developing a fault injection tool is describing the mechanism to inject, select, and activate a particular fault. In general, any fault injection tool consists of these three fundamental building blocks such as fault list manager, fault injection manager, and a result analyser as explained in Chapter 2.

HDL has been involved in improving various methodologies related to digital system testing during the last few decades. This improvement reduces the gap between the tools and methodologies used by design and test engineers.

The design engineers can check and test the systems at an early stage of the development cycle. There is no need to convert the designs into a compatible format¹⁶³.

Verilog HDL is one of the most widely used languages for implementing the design structure for ASIC and FPGA-based designs¹⁶⁴. These designs

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163 [Nav10] Navabi. Digital System Test and Testable Design Using HDL Models and Architectures. 2010

164 [BEJ15] Ben Fekih, Elhossini, and Juurlink. Applied Reconfigurable Computing.

2015

Figure 4.1: Fault injection techniques at various stages of the FPGA development flow.

are often written in HDL, and a bit-stream file is created to implement the circuit, which is downloaded into the FPGA chip. The FPGA development flow consists of several processes, e.g. synthesis, translate, place & route, and then a bit-stream generation. Many fault injection tools have been devised in the past several years for FPGA-based designs. These tools work on different stages of the development flow¹⁶⁵,¹⁶⁶ as manifested in Figure 4.1. It portrays the way of injecting faults at various stages of the FPGA development flow.

Fault injection tools for FPGA designs are classified into two main categories and subdivided shown in Figure 4.2.

The primary goal is to develop a fault injection tool, which performs fault injection analysis, fault simulation/emulation, testing, and dependability analysis directly on HDL designs for FPGAs and ASICs. Working on the code-level can reduce the gap between the tools and methodologies used by design and test engineers which speed-up the process of testing, produce cost-effective methods and reduce the time to market. In this chapter, code-modification technique of the RASP-FIT tool for various abstraction levels is presented.

This chapter is organised as follows. Section 4.2 presents the background information of techniques and tools for FPGA systems. Section 4.3 explains

165 [KHB16a] Khatri, Hayek, and Börcsök. Applied Reconfigurable Computing. 2016

166 [KHB17] Khatri, Hayek, and Börcsök. “Validation of selecting SP-values for fault models under proposed RASP-FIT tool”. 2017

FPGA-based FI tools

Simulation-based

Code Modification

Simulator Command

Emulation-based

Instrumentation-based

Reconfiguration-based

Figure 4.2: FPGA-based fault injection techniques and tools.

the different fault models developed and used throughout this dissertation.

Development of the tool RASP-FIT for Verilog HDL designs, written at various abstraction levels, is introduced in Section 4.4. Description of the graphical user interface for the proposed tool is given in Section 4.5. Results are presented in Section 4.6. In the end, Section 4.7 concludes the chapter.