Fault Injection at Code Level

As described earlier, the fault injection technique requires a faulty module of the original designs. The fault injection algorithm modifies the Verilog HDL code for the FPGA-based systems written at different abstraction levels such as:

• Gate abstraction level

• Data-flow abstraction level

• Behavioural abstraction level

Fault injection algorithm is also referred to as Verilog code modifier in the dissertation. It divides the code into two parts, i.e. declaration part and structural part. From the declaration part, it received the information about the variable’s types (e.g. input, output, wire, reg, parameters and others), their lengths and stored them in the container for the design. Verilog code modifier does not inject faults in the declaration part. However, in the structural part, faults are injected into the variables. For each abstraction level, the design is described in a particular way. Hence, faults are also injected differently at each abstraction level. Verilog code modifier reads the code line by line and extracts the keyword, matches it with the libraries and injects faults accordingly. Verilog code modifier can inject faults in both the combinational and sequential digital designs.

Verilog HDL defines the variable as scalars or vectors. Vectors can be further divided into bit-select or part-select or full vector length. Verilog code modifier under the RASP-FIT tool can inject faults in full vector length, bit-select of the vector or part-select of the vector. This is a significant feature in the RASP-FIT

tool, which is not seen/available in the state-of-the-art fault injection tools.

Verilog code modifier injects faults in all possible locations, and three fault models are used at this stage of development. It can generate several copies for different fault simulation applications to speed-up the simulation process.

Another primary feature is evenly distributing the fault in each faulty version of the original design. It also includes the mechanism to select and activate the injected faults (FISA³⁸⁰ control unit) sequentially.

This FISA control unit is based on the de-multiplexer logic circuit. As the number of faults increases for the system under test, the Verilog HDL code for it becomes large. The RASP-FIT tool adds the code for FISA control unit in each faulty design. The user does not need much effort to do a project and simulate the designs because the RASP-FIT generates the compilable faulty code. The RASP-FIT tool has a simple and user-friendly graphical user interface. Fault injection algorithm performs modification of the design in a short time. Unfortunately, this parameter is not measured for the state-of-the-art tools in the literature. The fault injection analysis for all benchmark design is performed on the RASP-FIT tool which runs on Intel(R) Core(TM) i7 CPU

@ 3.40 GHz as a standalone application developed using Matlab R2017 and the results are presented in Chapter 4.

It is seen that the stuck-at fault model is used in state-of-the-art tools.

The stuck-at fault model consists of two faults at wire or line, which are stuck-at 1, or stuck-at 0. Therefore, for the N locations in the SUT, we can inject 2N stuck-at faults. Table 8.1 shows the number of faults used in the experimentations. Work 1³⁸¹ and work 2³⁸² presented the number of fault locations for the ISCAS’85 benchmark designs for stuck-at fault model in the fault injection experimentation. The RASP-FIT tool works on the stuck-at fault model and bit-flip fault model. Hence, in this work, for N locations of faults, the RASP-FIT injects 3N faults in fault injection experimentation.

In a nutshell, the Verilog code modifier under the RASP-FIT tool helps design and test engineers to perform many fault simulation, testing and veri-fication applications in a short time and with a little effort. It also provides the code with a lesser number of extra port pins as compared to the technique presents in³⁸³. The fault control unit approach provides high controllability and observability. The RASP-FIT tool injects a single gate for each fault in

380Fault Injection Selection and Activation

381 [Zha12] Zhang. “Diagnostic Test Pattern Generation and Fault Simulation for Stuck-at and Transition Faults”. 2012

382 [Hab+14] Habib et al. “Don’t cares based dynamic test vector compaction in SAT-ATPG”. 2014

383 [DN11] Dunbar and Nepal. “Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults”. 2011

Table 8.1: Injection of fault in locations in the design

SUT Work 1 [Zha12] Work 2 [Hab+14] Proposed Work Total Fault Locations Total Fault Locations Total Fault Locations

c17 22 22 36

c432 524 524 1008

c499 758 758 1224

c880 942 942 2187

c1355 1574 1574 3192

c1908 1978 1878 4494

c2670 2747 2746 6456

c3540 3428 3425 8817

c5315 - - 13158

c6288 7744 - 14400

c7552 7550 - 18435

the design, which adds the small area-overheads as compared to the tools in the literature. Fault Injection TOol (FITO)³⁸⁴,³⁸⁵ developed to perform fault injection experiments for Verilog HDL at the gate level and RTL level as shown in Figure 8.1 along with the code modification at the various locations in the code as test_points.

Instead of the features as mentioned above in this novel approach, there are few challenges with the fault injection algorithm. The first and most important is that the Verilog code modifier considers each module as a separate design.

It can not be able to inject faults in design, which consists of many modules or hierarchical designs. It can inject faults in each module separately. Also, at the behavioural abstraction levels, Verilog code can contain macros, but the feature which reads macros is not yet added to the RASP-FIT tool.

To validate the claims as mentioned above, various benchmark designs are considered for fault injection modifications such as ISCAS’85, ISCAS’89, EPFL and few behavioural designs. The RASP-FIT tool generates a faulty design with the injection of different fault models.

384 [SSM08] Shokrolah-Shirazi and Miremadi. “FPGA-Based Fault Injection into Synthesizable Verilog HDL Models”. 2008

385 [SMS13] Shirazi, Morris, and Selvaraj. “Fast FPGA-based fault injection tool for embedded processors”. 2013

Figure 8.1: Different fault models in Verilog code and their schematics [SSM08].

8.3 Proposed ATPG Method with Hybrid