Bits Name Description
High-order Address bits. These are the 8 address bits of the 7-0 HAD buffer to which this descriptor points. They are written by the
host. The NCR92C990 does not change these bits.
End of Packet. This is the last buffer used by the NCR92C990 8 EOP for this packet. If EOP and SOP are both set, the packet fits
into a single buffer. EOP is set by the host. The NCR92C990 does not alter EOP.
Start of Packet. This is the first buffer used by the
NCR92C990 for this packet. If EOP and SOP are both set, the 9 SOP packet fits in one buffer. SOP must = 1 in the first buffer of a packet or it will be skipped over during a pull until the OWN bit and SOP bits are set.
Deferred. This means that the NCR92C990 had to defer while 10 DEF trying to transmit a packet. This occurs if the channel is busy
when the NCR92C990 is ready to transmit.
11 ONE One. This means that exactly one retry was necessary to transmit a packet. ONE is not valid if LCOL is set.
12 MOR More. This means that more than one retry was necessary to transmit a packet.
13 res Reserved. The NCR92C990 writes a zero to this bit.
14 ERR Error. This bit is set when at least one of the following bits is set: RTY, CLOS, LCOL, orUFL.
Rev. 1.0
SBus //0 Chipset Data Manual
NCR89C100 Page 4-25
NCR89C100 Page 4-26
Bits Name Description
This bit shows ownership of the descriptor entry. If OWN = 0, the host owns this entry. If OWN = 1, the NCR92C990 owns 15 OWN this entry. The host sets this bit after emptying the buffer to
which this descriptor points. The NCR92C990 clears this bit after filling the buffer. Once either the host or NCR92C990 has given over a buffer, it must not alter the descriptor entry.
Transmit Descriptor 2
15 14 13 12 11
o
1 1 1 1 BBL
Bits Name Description
Buffer Byte Length. This represents the length of the buffer 11-0 BBL to which this descriptor points. This number is expressed as a
two's complement. BBL is written by the host. The NCR92C990 does not change BBL in any way.
15-12 1 These bits must be ones. This field is written by the host. The NCR92C990 does not change these bits.
Transmit Descriptor 3 15 14
BUF UFL
Bits Name
9-0 TDR
10 RTY
13 12 11 10 9
o
res
I
LCOLI
CLOSI
RTY TDRDescription
Time Domain Reflectometry. This bit shows the state of a counter internal to the NCR92C990. This counter counts from the start of a transmission to a collision if one occurs. This value can be used to determine the approximate distance to a fault in a cable. TDR is valid and written by the NCR92C990 only if RTY is set.
Retry. This error indicates that the transmitter has failed because of collisions in 16 attempts to successfully transmit a packet. If the Disable Retry (DRY) bit in the mode register is set, RTY will set after only one failed transmission attempt.
Rev. 1.0 SBus 110 Chipset Data Manual
NCR92C990 EthernetllEEE 802.3 LAN Controller
Bits Name Description
Carrier Loss. This bit is set when the carrier input to the NCR92C990 goes low during a transmission. The NCR92C990 11 CLOS does not try again when it loses the carrier; it transmits the
entire packet until complete. CLOS is not valid during inter-nal loopback.
Late Collision. This bit means that a collision occurred after 12 LCOL the channel slot-time (64 bytes) elapsed. The NCR92C990
does not retry on late collisions.
13 res Reserved. The NCR92C990 sets this bit to O.
Underflow. This error indicates that the transmitter has shortened a message because the data was late coming from 14 UFL memory. UFL indicates that the temporary buffer emptied
before the end of the packet. The transmitter is turned off and TON set
=
O.Buffer Error. This bit is set during transmission when the NCR92C990 cannot find the EOP
=
1 in the current buffer 15 BUF and does not own the next buffer. BUF is set by theNCR92C990 and cleared by the host. If a buffer error occurs, an underflow error also occurs. The transmitter is turned off and TON set
=
O.NCR92C990 Changes and Differences to the Am7990
Rev. 1.0
In engineering the NCR92C990, NCR noticed discrepancies in the way the Am 7990 operated and the way the documentation read. A summary follows of these items that are most significant to hardware and software designers.
Documented
1. The Am.7990 documentation states that the initialization block must begin on an even word address. Odd-byte initialization addresses cause the Am7990 to operate in an undefined manner.
The NCR92C990 accepts odd-byte initialization block addressing in addi-tion to the standard even-byte addressing. In odd-byte addressing, the address increments by one after the first DMA transfer from the odd-byte address to get on an even boundary. Then the address counter increments by two, as with even-byte addressing.
2. The Am.7990 documentation states that no DMA bursts occur between polling and loading of DMA cycles. Under certain circumstances, the Am7990 actually performs DMA bursts between the polling and loading DMA cycles (ring accesses).
The NCR92C990 is designed to operate as the Am.7990 does, not as the documentation indicates.
Undocumented
1. The Am.7990 asserts the INTRb output 25.5 cycles after the rise of
SBus lID Chipset Data Manual
NCR89C100 Page 4-27
NCR89C100 Page 4-28
HOLDb on the last initialization DMA read cycle.
The NCR92C990 asserts INTRb after completing 1.5 cycles after the rise of the HOLDb output on the last initialization DMA read cycle.
2. Because of timing differences in the response time to a receive-based col-lision and the transfer of received data to the FIFO, responses may differ on the NCR92C990 if the collision signal is asserted during the header, between the destination and source addresses of a receive packet, or dur-ing the 64th data byte. In the first case, the lack of a sync bit causes the abort. In the second case, an address mismatch causes the abort. In the third case, a runt packet causes a CRC and framing error. It is possible for one of these aborts or errors in the Am 7990 to appear as one of the others in the NCR92C990.
3. When the first DMA transfer is a data word, the Am7990 starts transmis-sion eight cycles after the rising edge of the DASb pulse. If the first DMA transfer is only a byte, the Am7990 starts the transmission 12 cycles after the rising edge of the DASb pulse.
In both the byte and word cases, the NCR92C990 starts transmission eight cycles after the rising edge of DASb.
4. During loopback, the rising edge of the DASb pulse latches in the last byte/word of a transmission. The Am 7990 begins transmission of the next packet preamble on the rising edge of DASb.
The NCR92C990 begins transmission within five clock cycles after the rising edge of DASb.
5. During externalloopback, the Am7990 SILO can lose some data if there is heavy traffic on the media.
The NCR92C990 does not lose data, even during heavy traffic on the media.
6. The Am 7990 generates a memory error if READYb has not been asserted within 254 cycles after DASb falls and both the transmitter and receiver are turned off. If READYb falls between 251 and 253 cycles after DASb falls, incorrect data is loaded into Control/Status Register 0, the memory error (ME) bit is set, but neither the transmitter nor receiver are turned off.
The NCR92C990 matches this behavior.
7. The Am 7990 requires 11 clock cycles after the rising edge of HOLDb to set the missed packet (MP) bit in Control/Status Register O.
The NCR92C990 sets the MP bit within two clock cycles of the rising edge of HOLDb.
8. If the SILO overflows during a receive operation, the Am7990 updates the ring with the number of bytes actually transferred to memory at that point.
Rev. 1.0 SBus I/O Chipset Data Manual
Rev. 1.0
NCR92C990 EthemetllEEE 802.3 LAN Controller
The NCR92C990 updates the ring with the number of bytes transferred to the memory, plus any that may be left in the FIFO when the overflow occurred. The data in the FIFO is not actually transferred to memory.
Because the packet is incomplete, the host should ignore all the data in the buffer, and the actual amount of data in the buffer should not be con-sidered.
9. The Am7990 begins Time Domain Reflectometry (TDR) counts from the assertion of RENA.
The NCR92C990 begins TDR counts 2-3 cycles after the assertion of TENA, as specified in the IEEE 802.3 specification.
TDR counts are only valid after a retry. During TX updates when a retry does not occur, the Am7990 writes invalid TDR values to the ring.
The NCR92C990 also writes invalid TDR data to the ring, but not neces-sarily the same values.
10. The Am 7990 recognizes a defer condition when it is ready to assert TENA at the start of transmission, but RENA is already asserted.
The NCR92C990 recognizes a defer condition when it is ready to assert TENA at the start of a transmission and either RENA is already asserted or the interpacket gap time has not elapsed since RENA went inactive.
11. If the SILO on the Am7990 contains 43 or more bytes of data from a pre-vious reception and another packet is being sent by another node on the network, an overflow condition can occur even if the second packet is not addressed to this node. For example: 43 bytes of data remain in the SILO from a previous packet reception. The Am7990 checks the incoming packet for a valid destination address and, in the process, tries to trans-fer the six address bytes to the SILO. It recognizes that the address is not its own after the sixth byte, but before that happens, an overflow of the 48-byte SILO occurs (43 + 6
=
49). The SILO pointer is reset to the 44th byte in the FIFO, but the packet residing in the SILO is labeled with an overflow error.The NCR92C990 temporarily stores the incoming destination address in a separate FIFO which is either erased if the address is not matched, or burst into the main 48-byte FIFO if the address is matched. No overflow is reported by the NCR92C990 in the previous example.
12. Defer is reported if the first attempt to transmit a packet is delayed because RENA is asserted when the NCR92C990 is ready to transmit (the IPG has expired and the TX FIFO contains at least one byte of data);
or, for an RX-TX transmission, defer is reported if the NCR92C990 is ready to transmit and the IPG time has not expired.
13. Interpacket gap: Either TX-TX or RX-TX.
In general, three conditions are required in order to begin a transmis-sion:
SBus 110 Chipset Data Manua'
NCR89C100 Page 4-29
• The backoff count is 0 (only pertains to retries)
• The IPG has expired.
• The TX FIFO contains at least 1 byte of data.
The Am7990 TX FIFO is reset (and thus empty) whenever RENA is asserted except when:
• TENA is also asserted, or
• RENA is still asserted from a previous transmission, or
• An RX packet is still on the network but the RX circuitry has deter-mined that it is not addressed to this node.
Therefore, the NCR92C990 will defer to any incoming packet, regardless of the state of the IPG counters except for a packet which causes RENA to be asserted just before TENA is to be asserted for transmission.
The NCR92C990 IPG counter will be reset if the RENA pulse is shorter than the remainder of the IPG as programmed. The IPG features control IPG timings which are different for RX-TX, TX-TX and the default IPG partition.
If the NCR92C990 is ready to transmit and is waiting for the IPG to expire, it will defer to the incoming packet thus avoiding a collision.
TX-TX
The Am7990 data sheet refers to the condition that if RENA is asserted within the first 4.1 ~s of the IPG after a TX that the Am7990 will defer to the packet and receive it if the sync bit is correctly recognized after the first 4.1 ~s of the IPG. The NCR92C90 will begin to look for the sync immediately.
RX-TX
The Am7990 data sheet refers to the condition that if RENA is asserted within the first 4.1 ~s of the IPG after a RX that the Am7990 will defer to the packet and not receive it. The NCR92C990 will defer to the packet and will receive it.
Electrical Specifications
NCR89C100 Page 4-30
Absolute Maximums
Symbol Parameter
TA
Ambient Temperature Ts Storage TemperatureVDD Supply Voltage
VIN Input Voltage
VOUT Output Voltage
TL Lead Temperature (Solder-ing 10 seconds maximum)
Minimum SBus 110 Chipset Data Manual
Rev. 1.0
NCR92C990 EthernetAEEE 802.3 LAN Controller
DC Characteristics
(Voo
=
4.75 to 5.25 V, Vss=
0 V, TA=
0° C to 70° C)Symbol Parameter Minimum Maximum Units
VIL Input Voltage, Low Vss- 0.5 0.8 Volts
VIH Input Voltage, High 2.0 VDD Volts
VOL Output Voltage, Low 0.4 Volts
(VDD
=
4.5 V)VOH Output Voltage, High
2.4 Volts
(VDD
=
4.5 V)CIN Input Capacitance 10 pF
ITL Input Leakage Current
t10 ~A
(VDD
=
5.5 V)IOL Output Leakage Current
tlO ~A
The following timing parameters apply strictly to the VS700H macrocell. These timings are derived from pre-layout estimated capacitances. Post-layout timing variations may occur.
6 TENA_OUT propagation delay after
1 25 ns
rising edge of TCLK
7 TENA_OUT hold time after TCLK
1 7 ns
rising
8 TX_OUT propagation delay after
1 32 ns
SBus 110 Chipset Data Manual.
NCR89C100 Page 4-31
(VDD
=
4.75 to 5.25 V, Vss=
0 V, TA=
0° C to 70° C) External load 1 pFrucIN data hold time from RCLK rising
ruCIN data setup time to RCLK rising RENA-IN low duration
CLSN_IN high duration
Bus master driver disable after rising edge of HOLDb_OUT
Bus Master driver enable after falling edge of HLDAb (Bus Master)
Delay from HOLDb_OUT to falling edge of HLDAb (Bus Master) RESETb pulse width low
Read/Write, AddresslData cycle time A(23:16) setup time to the falling edge of ALEb_OUT
A(23:16) hold time after the rising edge of DASb_OUT
DAL_OUT(15:0) setup time to falling edge of ALEb_OUT
DAL_OUT(15:0) hold time after falling edge of ALEb_OUT
Data setup time to the rising edge of DASb_OUT (Bus Master Read)
Data hold time from the rising edge of DASb_OUT (Bus Master Read)
Data setup time to falling edge of DASb_OUT (Bus Master Write) Data setup time to the rising edge of DASb_OUT (Bus Master Write)
Data hold time after the rising edge of DASb_OUT (Bus Master Write)
Data driver delay after the falling edge of DASb_IN (Bus Slave Read) (RAP) Data driver delay after the falling edge of DASb_IN (Bus Slave Read) (CSRO, 1,2,3)
Data hold time after the rising edge of DASb_IN (Bus Slave Read)
Data hold time after the rising edge of DASb_IN (Bus Slave Write)
Data setup time to the falling edge of DASb_IN (Bus Slave Write)
Fig. SBus 110 Chipset Data Manual
NCR92C990 EthernetREEE 802.3 LAN Controller
(VDD
=
4.75 to 5.25 V, Vss=
0 V, TA=
00 C to 700 C) External load 1 pFNum. Description Fig. Min. Type Max. Units
40 ALEb_OUT high pulse width 3,4 144 ns
41 Delay from rising edge ofDASb_OUT 3,4 100 ns to rising edge of ALEb_OUT
42 DASb_OUT low pulse width 3,4 252 ns
43 Delay from falling edge of ALEb_OUT
3,4 100 ns
to falling edge of DASb_OUT
Delay from rising edge ofDALOb_OUT
44 to the falling edge DASb_OUT (Bus 3 50 ns
Master Read)
Delay from falling edge READYb_IN to
45 rising edge ofDASb_OUT 3,4 55 255 ns
(Bus Master)
Delay from rising edge ofDALOb_OUT
46 to falling edge of DALIb_OUT (Bus 3 55 ns
Master Read)
47 DALIb_OUT setup time to rising edge
3,4 240 ns
of DASb_OUT (Bus Master)
48 DALIb_OUT hold time after the rising
3 8 ns
edge of DASb_OUT (Bus Master Read) Delay from rising edge of DALIb_OUT
49 to falling edge of DALOb_OUT (Bus 3 82 ns
Master Read)
50 DALOb_OUT setup time to the falling
3 150 ns
edge of ALEb_OUT (Bus Master Read) DALOb_OUT hold time after the
fall-51 ing edge of ALEb_OUT (Bus Master 3 50 ns
Read)
Delay from rising edge of DASb_OUT
52 to rising edge of DALOb_OUT (Bus 4 50 ns
Master Write)
53 CSb hold time after the rising edge of
5,6 0 ns
DASb_IN (Bus Slave)
54 CSb setup time to the falling edge of
5,6 0 ns
DASb_IN (Bus Slave)
55 ADR hold time after the rising edge
5,6 0 ns
DASb_IN (Bus Slave)
56 ADR setup time before the falling edge
5,6 0 ns
of DASb_IN (Bus Slave)
Delay from ALEb_OUT to falling edge 57 of READYb_IN to ensure a minimum
bus cycle time of 600 ns (See note on 3,4 395 ns page 34.)
58 Data setup time to the falling edge of
5 100 ns
READYb_OUT (Bus Slave Read)
Rev. 1.0
SBus //0 Chipset Data Manual
NCR89C100 Page 4-33
(VDD
=
4.75 to 5.25 V, Vss=
0 V, TA=
00 C to 700 C) External load 1 pFREADYb_IN hold time after the rising edge of DASb_OUT (Bus Master) READYb_OUT driver on after the fall-ing edge ofDASb_IN (Bus Slave Write) (RAP)
READYb_OUT driven on after the fall-ing edge ofDASb_IN (Bus Slave Write) CSRO, 1, 2, 3
READYb_OUT hold time after the ris-ing edge of DASb_IN (Bus Slave) READ_IN hold time after the rising edge ofDASb_IN (Bus Slave) READ_IN setup time to the falling edge ofDASb_IN (Bus Slave)
TCLK rising edge for low or high delay TCLK rising to valid address
TCLK rising edge to control signals active
TCLK falling edge to ALEb_OUT low TCLK falling edge to DASb_OUT fall-ing edge
READYb_IN setup time to TCLK (See note on page 34.)
TCLK rising edge to DASb_OUT high HLDAb setup to TCLK
RENA_IN hold time after the rising edge of RCLK_JN
REN~IN defer before TENA_OUT
REN~IN extended after RCLK_IN last falling
Delay from DASb .... OUT rising to HOLDb_OUT rising
READYb_OUT falling to DASb_IN ris-ing (Slave WritelRead)
ALEb_OUT falling to next ALEb_OUT falling (DMA Burst) (Not shown in diagrams)
DASb_IN falling to DAL_ENb falling (Slave) SBus 110 Chipset Data Manual
Rev. 1.0
NCR92C990 Ethernet/lEEE 802.3 LAN Controller
(VDD
=
4.75 to 5.25 V, Vss=
0 V, TA=
0° C to 70° C) External load 1 pFNum. Description Fig. Min. Type Max. Units
80 DASb_IN rising to DAL_ENb rising
5 2 6 ns
83 DALOb_OUT falling to D~ENb
fall-3 2 6 ns
ing (single DMA)
84 HLDAb falling to DAL_ENb falling
3 200 ns
'(single DMA)
85 DAL_ENb active to DAL_OUT stable
3,4 2 6 ns
(single DMA)
86 ALEb_OUT falling to DAL_ENb rising
3,4 52 ns
(single DMA)
87 DASb_OUT rising to ~ENb rising
3,4 100 ns
(single DMA)
88 DASb_OUT rising to DA_ENb rising
3 100 ns
(single DMA)
89 DA_ENb rising to ALEb_OUT rising
3 100 ns
(single DMA)
90 DAL_OUT hold time after DAL_ENb
3 20 ns
rising (Slave)
91 D~ENb falling to DASb_IN rising
5 100 ns
(Slave Read)
92 D~ENb falling from DASb_IN falling
5 100 ns
(Bus Slave Read)
93 DA-ENb falling from DASb_IN falling
6 100 ns
(Bus Slave Write)
NOTE: The READYb_IN setup time before negation ofDASb_OUT is a function of the synchronization time of READYb_IN. The synchronization must occur within 100 ns. The setup time is 100 ns plus any accumulated propagation delays. Ready slips occur on 100 ns increments. No wait states are added by the NCR92C990 if either parameter number 57 or 70 is met.
SBus lID Chipset Data Manual .
NCR89C100 Page 4-35