1 = Data strobe is bidirectional. Master write transfer protocol is selected.
o
= Data strobe is fIxed as an output. Master read/write transfer protocol is selected.This bit specifIes the data to be sourced during a memory clear operation. When set, the sourced data will be ones. When reset, the sourced data will be zeros.
MEM_CLR
This bit enables memory clear operation. Additionally, the DMA control registers need to be confIgured and DMA must be enabled.
Parallel Port Interface Registers Parallel Data Register (P _DR)
The Data Register is an 8-bit read/write port used to transfer data to and from the external device. In programmed I/O mode data written to this register is presented to the I/O pins if the DIR bit of the Transfer Control Register is
o.
A read of this register will result in the data previously written or if the DIR bit of the Transfer Control Register is set to 1, the latched data from the last data strobe. The data port is not accessible via slave write cycles during DMA (P _DMA...ON=l). Any write cyclesSBus I/O Chipset Data Manual
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during DMA will not generate errors, the data will simply not be written. Since both DMA and PIO share the same data register, internalloopback is possible by running a single byte DMA cycle followed by a PIO cycle to verify the data. This will test both the DMA and slave data paths.
The reset state of this register is undefined.
ADDR=14, Slze=8 Bit
Addr Bits Description Size Type
14 7:0 Parallel Data 8 Bit RIW
Transfer Control Register (P _ TCR)
The Transfer Control Register is an 8-bit register whose contents definelreflect the state of the external interface handshake and direction control signals. The DS, ACK, and BUSY· bits will reflect the state of the external pins, when read. Writing these bits defines a value to be driven onto the external pins if the individual direction select bits (DS_DSEL, ACK,..DSEL, BUSY_DSEL) and the direction control bit (Dffi) are configured such that these pins are outputs. The write bits and read bits are different. That means that values typically written to these bits may not be reflected on a read cycle. However, by setting the EN_DIAG bit of the Operation Control Register, these register bits become read/write (see the EN_DIAG bit description of the OCR).
ADDR=15, Size=8 Bit
Bit Mnemonic Description Type
0 DS Data Strobe. RIW
1 ACK Acknowledge. RIW
2 BUSY Busy (active low). RIW
3 DIR Direction Control. 0= Write to external Device. 1 =Read. RIW
4
-
Unused. Reads aso.
RO5
-
Unused. Reads as O. RO6
-
Unused. Reads as O. RO7
-
Unused. Reads aso.
RODS
Reading this bit reflects the state of the bidirectional p_d_strb pin. Writing this bit with DS_DSEL=O or with DS_SEL=1 and Dffi=O will cause the value written to be driven onto p_d_strb. The reset state of the output latch is 0, but the value read back from this bit after reset will reflect the input signal being driven onto p_d_strb.
ACK
Reading this bit reflects the state of the bidirectional p_ack pin. Writing this bit with ACKJ)SEL=1 will cause the value written to be driven onto p_ack ifDffi=l. The reset state of the output latch is 0, but the value read back from this bit after reset will reflect the input signal being driven onto p_ack..
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DMA2 DMA Core
BUSY
Reading this bit reflects the state of the bidirectional p_bsy_ pin. Writing this bit with BUSY_DSEL=l will cause the value written to be driven onto p_bsy _ if DIR=l. The reset state of the output latch is 0, but the value read back from this bit after reset will reflect the input signal being driven onto p_bsy_.
DIR
This bit defines and controls the direction of data transfer: O=write to external device, 1= read from external device. It is also driven externally on the p_d_dir_ pin. Note that this bit also controls the direction ofDMA (except in the case of a memory clear operation, when the MEM_CLR bit defines DMA direction). The state of the DIR bit is reflected in the P _ WRITE bit of the P _CSR. Reset state of this bit is 1.
Output Register (P _OR)
The Output Register is an 8-bit read/write register whose contents are driven onto the corresponding external pins. In diagnostic mode (EN_DIAG=l), bits 0-2 are gated onto Input Register bits 0-2. The external outputs remain low while diagnostic mode is enabled. All bits are 0 after reset.
ADDR=16, Size=8 Bit
Bit Mnemonic Description Type
0 SLCT_IN Select in. This bit is output on the RIW p_slcLin pin.
1 AFXN Auto Feed. This bit is output on the p_afxn pin. RIW
2 INIT Initialize. This bit is output on the RIW p_init pin.
3
-
Reserved RIW4
-
Reserved RIW5
-
Reserved RIW6
-
Unused. Reads as 0 RO7
-
Unused. Reads as 0 ROInput Register (P _IR)
The Input Register is an 8-bit read/write register whose contents reflect the state of several external input pins and their corresponding interrupts. In diagnostic mode (EN_DIAG=l), bits 0-2 are driven from output register bits 0-2.
ADDR=17, Slze=8 Bit
Bit Mnemonic Description Type
0 ERR Error input. This bit reflects the state of the err input pin. RO
1 SLCT Select input. This bit reflects the state of the slct input pin. RO
2 PE Paper empty. This bit reflects the state of the p_pe_ input pin. RO
3
-
Unused. Reads as 0 ROSBus //0 Chipset Data Manual
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Bit Mnemonic Description Type
4
-
Unused. Reads as 0 RO5
-
Unused. Reads as 0 RO6
-
Unused. Reads as 0 RO7
-
Unused. Reads as 0 ROERR, SLCT, PE
These bits reflect the state of the corresponding input pins.
Interrupt Control Register
This 16-bit read/write register is used to specify operation of the parallel port interrupts. Interrupt enables, polarity, and IRQ pending bits are contained in this register. The detailed function of these bits is described following the table. Reset value of this register is all bits
o.
When set, enables ERR interrupts. RIW ERR interrupt polarity. l=on rising
edge, O=on trailing edge. RIW
When set, enables SLCT interrupts. RIW SLCT interrupt polarity. l=onrising
edge, O=on trailing edge. RIW
When set, enables PE interrupts. RJW PE interrupt polarity. l=on rising
edge, O=on trailing edge. RJW
When set, enables BUSY interrupts. RIW BUSY interrupt polarity. l=on rising
edge, O=on trailing edge. RJW
When set, enables ACK interrupts on rising edge of ack. RJW
When set, enables DS interrupts on the rising edge of ds. RJW
When set, error IRQ pending. RIW1 When set, select IRQ pending. RIW1 When set, paper empty IRQ pending. RIW1 When set, busy IRQ pending. RlW1 When set, acknowledge IRQ pending. RIW1 When set, data Strobe IRQ pending. RIW1
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*_IRQ_EN
When set, enables interrupts on the corresponding bits of the Input and Transfer Control registers. Note that the interrupt enable bit of the PD_SCR must also be enabled to allow a hardware interrupt to be generated.
*_IRP
Defines the polarity of the edge triggered interrupts on the corresponding bits of the Input Register. O=Interrupt generated on the 1 to 0 transition of the signal. 1=
Interrupt generated on the 0 to 1 transitions of the signal. Note that when configuring the interrupt polarity of a given signal, it is possible to generate a false interrupt. It is suggested that when the interrupt polarities are being programmed, interrupts be disabled and all interrupt sources be cleared upon completion of programming.
ERR_IRQ, SLCT _IRQ, PE_IRQ, BUSY_IRQ
When set, an interrupt is pending on the corresponding bit. The interrupt is cleared and the bit is reset when a one is written to the corresponding bit. Writing a 0 to these locations leaves the bit(s) unchanged.
ACK_IRQ
When set, an interrupt is pending due to the receipt of p_ack. The interrupt is set on the 0 to 1 transition of p_ack. This interrupt is intended to facilitate PIO transfers while configured as master under master write protocol. The interrupt is cleared and the bit is reset when a one is written to this bit. Writing a 0 to this location leaves the bit unchanged.
OS_IRQ
When set, an interrupt is pending due to the receipt of p_«t-strb. This interrupt is intended to facilitate PIO transfers while configured as slave under master write protocol. The interrupt is cleared and the bit is reset when a one is written to this bit.
Writing a 0 to this location leaves the bit unchanged.
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Parallel Port Programming Notes
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Parallel Port Interrupts
The P _INT_PEND and P _ERR_PEND bits of the P _CSR reflect whether the PP has an interrupt source active or not. This will allow software to determine whether an interrupt is pending on the PP by performing one register read. If P _INT_PEND is set, then one or more of the following interrupt sources are active:
Parallel Port Control/Status Register (P _CSR):
• P _TC - Terminal Count.
Par~llel Port Interrupt Control Register (P _ICR):
• ERR_IRQ - Error
• SLCT_IRQ - Select
• PE_IRQ - Paper Error
• BUSY_ffiQ - Busy
• AC~IRQ - Acknowledge
• DS_IRQ - Data Strobe
If the P _ERR_PEND bit is set, the P _RESET must be toggled to reset the parallel port to recover from the error.
Mode Selection
When switching modes of operation of the parallel port, the P J>MA...ON bit should be
o
and the IDLE bit of the Transfer Control Register should be 1 before the mode is switched. This insures that no data transfer cycles are in progress. ''Mode Selection"in this context means handshake specification, control signal direction selection, interface direction selection via the nffi bit of the Transfer Control Register, and mem-ory clear operations.
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