Rev. 1.0
A(23:16) - High-Order Address Bits.
During the bus master address segment of a memory transfer, these out-puts contain the most significant eight bits of the 24-bit address. A_ENb is the enable for A(23:16).
ADR - Register Address Port Select.
This input selects which internal register is in use during a slave mode access. If ADR = 1, the register address port is selected. If ADR
=
0, the register data port is selected.ALEb_OUT - Address Latch Enable/Address Strobe.
This output demultiplexes the address bus. ALE is programmed through the ACON bit of Control/Status Register 3.
BMOb_OUT and Bmlb_OUT - Byte Selection BMO_OUT BM1b_OUT Mode
0 0 16-bit word
0 1 upper byte
1 0 lower byte
1 1 not used
CSb - Chip Select.
To select the NCR92C990 for slave access, drive this input low. CSb must remain active throughout the complete cycle.
SBus liD Chipset Data Manual
NCR89C100 Page 4-7
NCRB9C100 Page4-B
CLSN_IN - Collision.
This input from the Manchester Encoder/ Decoder (MENDEC) indicates a collision was detected.
DAL_OUT(15:0) - DAL_IN(15:0) - Address/Data Line.
During the address segment of a memory transfer, this split bus contains the lower 16 bits of memory address. During data read/write segments, this split bus contains 16 bits of data. DAL_ENb is the enable for DAL_OUT(15:0).
DALIb_OUT - External data bus transceiver control.
This output is active in bus master mode only. It is asserted when DAL_OUT(15:0) is driven. DALIb_OUT = 1 during a write cycle.
DALIb_OUT
=
0 during the DATA segment of a read cycle.DALOb_OUT - External data bus transceiver control.
This output is active in bus master mode only. It is asserted when DAL_OUT(15:0) is driven. DALOb_OUT
=
0 during a write cycle and the ADDRESS segment of a read cycle.DASb_OUT - Data Strobe.
This output identifies the data segment of the bus cycle. DASb_OUT
=
0during the WRITE data segment of the bus master transfer.
DASb_OUT = 1 during the address segment of the bus master transfer. A low-to-high transition is used to latch WRITE data for a slave cycle.
DASb_IN - Data Strobe.
This input identifies the data segment of the bus cycle. DASb_IN
=
0dur-ing the READ data segment of the bus master transfer. DASb_IN
=
1dur-ing the address segment of the bus master transfer. A low-to-high transition is used to latch data READ.
HLDAb - Hold Acknowledge.
When this input, HLDAb
=
0, in response to an assertion ofHOLDb_IN, the NCR92C990 is the bus master. The controller waits for HLDAb to go high before reasserting HOLDb_OUT=
O.HOLDb_OUT - Hold Request.
The NCR92C990 asserts this active low output during memory accesses.
It stays
=
0 for the entire burst. This pin is programmable through bit 0 of Control/Status Register 3.HOLDb_IN - Hold Request Sense.
The NCR92C990 looks at HOLDb_IN input to sense the HOLDb condi-tion. If HOLDb_IN
=
1 the NCR92C990 can drive HOLDb_OUT=
0 torequest the bus.
INTRb_OUT - Interrupt.
This active low output activates when any interrupts are generated according to the flags set in Control/Status Register
o.
INTRb_OUT is disabled through bit 6 of Control/Status Register O. (In which case INTRb_OUT will remain high.)Rev. 1.0 SBus 110 Chipset Data Manual
Rev. 1.0
NCR92C990 EthemetllEEE 802.3 LAN Controller
RCLK_IN - Receive Clock.
This input is the 10 MHz receive clock from the MENDEC.
READ_IN - Read Data In.
This input is used to define the read/write operation. For a slave cycle READ_IN = 0 to output data (write). READ_IN = 1 to input data (read).
Cycle READ_IN Type
0
Slave Data output
1 Data input
READ_OUT - Read Data Out.
This output is used to define the read/write operation. For a master cycle READ_OUT
=
1 to input data (read), READ_OUT=
0 to output data (write).Cycle READ_OUT Type
1
Bus Master Data output
0 Data input
READYb_IN - Ready (Master mode).
This active low input in a bus master mode is used to provide an asyn-chronous acknowledgment that a transfer can be performed. The
READ_OUT signal determines whether a read or write transfer is taking place.
READYb_OUT - Ready (Slave mode).
Asserted active low output is generated in response to DASb_IN for a Slave read or write. The READ_IN signal determines whether a read or write transfer is taking place.
RENA_IN - Receive Enable.
This buffered input from the MENDEC signifies a carrier present.
RESETb - Reset.
This active low buffered input is a system reset for the NCR92C990 macrocell.
RX..IN - Receive Data.
This is the buffered receive data input from the MENDEC data output.
TBUS(17:0) - Test Bus Outputs.
These outputs are used for testing and are always driven.
TCLK - Transmit Clock.
This buffered input is the system clock from the MENDEC.
TENA_OUT - Transmitter Enable.
This is an output to the MENDEC to enable the MENDEC transmitter.
SBus 110 Chipset Data Manual .
NCR89C100 Page 4-9
TESTb - Test Mode Enable.
This active low input is driven low to enable the NCR92C990 internal test features. TESTb should be driven high for normal operation.
TESTRb - Test Mode Enable.
This active low input is driven low to enable the NCR92C990 internal test features. TESTRb should be driven high for normal operation.
TX_OUT - Transmit Data.
This output is the transmit data to the MENDEC.