Figure 4·2 Macrocell Functional Block Diagram Silo
Mode Register
Central Controller
.... 1 - -_ _ ---1
LAN Interface
Rev. 1.0
The NCR92C990 supports error reporting for diagnostics, addressing, collision, babbling transmitter (jabbering), packet framing, overflow and underflow.
Diagnostic Modes
Internal and externalloopback modes are supported by the NCR92C990; they are configured through the internal registers.
Addressing Modes
Physical, logical and promiscuous modes are supported.
Physical
Packets can be received that have the full 48-bit destination address matching the physical address that is programmed into the NCR92C990 during initialization.
SBus I/O Chipset Data Manual
NCR89C100 Page 4-11
Logical
Packets can be received only if the destination address matches one of 64 logical addresses programmed in the logical address filter at initialization.
Promiscuous
A promiscuous mode allows reception of all packets. All incoming, error-free pack-ets are accepted and stored in the buffer memory regardless of destination address or length.
Collision Detection
The NCR92C990 supports collision detection and recovery for both transmit and receive functions.
Transmitting
Upon a collision during transmit, the NCR92C990 will jam with 1 bit for 32 bit-times and then back off for a multiple number of slot-bit-times. A slot-time is equal to 512 bit-times @ 10 MHz/100 ns periods. The delay for the next transmission is cho-sen from a uniformly distributed random integer in the range of 1 to 2k where k=1,2,3, ... n. Collisions during preamble, destination or source address fields, data fields, and CRC are handled in the same manner.
Receiving
Upon a collision during receive, the packet reception terminates immediately. A collision that occurs before the 64-byte interval results in a runt packet. A collision that occurs after the 64-byte interval causes a truncated packet that is transferred to memory. A CRC error is reported in this case.
Descriptor Ring Management
Buffer management for the NCR92C990 is handled by a recurrent list of assign-ments in memory called descriptor rings. There are separate descriptor rings for both transmit and receive. The NCR92C990 searches the descriptor rings to deter-mine the next empty buffer. Mer an empty buffer is filled, the OWN bit is set in that descriptor ring. When a descriptor ring has its OWN bit set, the NCR92C990 starts a DMA transfer using the descriptor ring buffer pointer which points to the data memory buffer.
Internal Registers
NCR89C100 Page 4-12
Initialization Block
The NCR92C990 reads a data structure in memory to initialize pointers to mem-ory transmit and receive buffers. This sets the mode of operation, and reads the logical address filter programming as well as the controllers physical address on the network. The initialization data structure contains the following:
• •
• •
•
Mode register Physical address Logical address filter
Receive ring address pointer and length Transmit ring address pointer and length
Rev. 1.0 SBus I/O Chipset Data Manual
Mode Register
SBus //0 Chipset Data Manual
NCR92C990 EthernetllEEE 802.3 LAN Controller
5 4 3 2 1
o
DRY COL DTC LBK DTX DRX
Description
Disable Receiver. When this bit is set, the NCR92C990 rejects all incoming packets because the receive descriptor ring is not accessed. DRX
=
1 will clear the RON bit in Con-trol/Status Register 0 when initialization is done.Disable Transmitter. When this bit is set, the NCR92C990 does not access the transmit descriptor ring so no transmis-sions are attempted. DTX
=
1 will clear the TON bit in Con-trol/Status Register 0 when initialization is done.Loopback. Loopback allows the NCR92C990 to transmit a packet addressed to itself which can be used to test the LAN interface at various levels. The packet size is limited to 8-32 bytes with 4 bytes allowed for CRC when DTC
=
O. Runtpacket detection is disabled. TBK
=
1 allows concurrent transmit and receive for a packet length constrained to fit in the SILO. Transmission will begin when the entire packet is in the SILO. The entire received packet will be written to memory only after reception is complete. Transmit data chaining is not allowed in LBK mode. Receive data chaining is allowed if the receive packet length does not exceed 32 bytes.Disable Transmit CRC. When DTC
=
0, the transmitter gen-erates and appends CRC to the transmitted packet. When DTC=
1, no CRC is appended to the packet. During LBK mode, DTC=
1 will cause CRC to be appended to the trans-mitted packet. Receive CRC will be checked by theNCR92C990 and written into memory. DTC
=
1 disables CRC append during transmit. The host must append the CRC to the transmit packet in this case. Receive CRC will be checked.Force Collision. This bit allows testing of the collision logic.
The NCR92C990 must be in internalloopback mode for COL to be valid. If COL
=
1, a collision will be forced during the next transmit and can result in 16 transmission retries.Transmit Descriptor 3 RTY will be set
=
1 in this case.Disable Retry. When DRY
=
1, the NCR92C990 attempts to transmit a packet only once. If there is a collision on this first attempt, a retry error is reported. In Transmit Descriptor 3, RTY=
1.NCR89C100 Page 4-13
NCR89C100 Page 4-14
Bits Name Description
Internal Loopback. This is set with the LBK bit to determine where the loopback function is done. The NCR92C990 does not receive any external packets when it is in internal loop-6 ILB back mode. The packet size is limited to 8-32 bytes. Extend packet reception is disabled. Muticast addressing in External Loopback (LBK) is valid only when DTC = 1. Received pack-ets will be accepted from the network. ILB is valid only when LBK= 1.
LBK ILB Loopback Mode
0 X Normal Mode
1 0 External Loopback
1 1 Internal Loopback
Bits Name Description
14-7 res Reserved.
15 PRO Promiscuous mode. When PRO = 1, all incoming packets are accepted.
Physical Address (PADR)
The physical address is the unique 48-bit physical address assigned to the NCR92C990. PADR (0) must = O.
Logical Address Filter (LADR)
The logical address filter is a 64-bit mask used by the NCR92C990 to accept logical addresses. It is composed offour 16-bit registers. The logical address filter is a 64-bit mask used to qualify incoming packets. After the 48 bits of the destination address have gone through the LADR CRC circuit, the high order 6 bits of the 32-bit LADR CRC value are set to select 1 of 64 bit positions in the Logical Address filter. If a bit position in the logical address filter = 1, the packet will be accepted.
Broadcast addresses (all ones) pass transparently through the logical address fil-ter. If the logical address filter (LADR) = 0, all packets are rejected except Broad-cast packets.
Receive Ring Pointer
31·29 28-24 23·3
RRL res RRA
2 zero
1
o
zero zero
Rev. 1.0 SBus 110 Chipset Data Manual
NCR92C990 EthernetllEEE 802.3 LAN Controller
Bits Name Description
2-0 zero These bits must be zero. Receive Ring Pointers are quad word boundary aligned.
23-3 RRA Receive Ring Address. These bits are the lowest address bits of the receive ring.
28-24 res These bits are reserved for internal use.
31-29 RRL Receive Ring Length. This is the number of entries in the receive ring expressed as a power of two.
RRL Number of Entries
0 1
1 2
2 4
3 8
4 16
5 32
6 64
7 128
Transmit Ring Pointer
Bits Name 2-0 zero 23-3 TRA 28-24 res 31-29 TRL
Rev. 1.0
SBus //0 Chipset Data
Manual-31-29 28-24 23-3 2 1
o
TRL res TRA zero zero zero
Description
These bits must be zero. Transmit Rings are aligned with quad word boundaries.
Transmit Ring Address. These bits are the lowest address bits of the transmit ring.
These bits are reserved for internal use.
Transmit Ring Length. This is the number of entries in the transmit ring expressed as a power of two.
TRL Number of Entries
0 1
1 2
2 4
NCR89C100 Page 4-15
TRL Number of Entries
3 8
4 16
5 32
6 64
7 128
Control/Status Registers
NCR89C100 Page 4-16
The Control/Status registers are accessed through the register address port and the register data port. The status register being accessed is determined by the value of the ADR input. When ADR
=
0, the register data port is selected and when ADR=
1, the register address port is selected.The address of the Control/Status register to be accessed is written to the register address port. All subsequent reads and writes to the data port have the same data read/written to the selected Control/Status register.
Register Address Port
15 2 1 0