Lec e No e in Info ma ic (LNI), Ge ell chaf fÈ Info ma ik, Bonn 15
Pa i -ba ed Sof E o De ec ion i h Sof a e-ba ed Re . T iplica ion-ba ed Sof E o Co ec ion - An Anal ical Compa i on on a Fla h-ba ed FPGA A chi ec e
GÈokcËe A do 1GÈo ch in Fe 1
Ab ac :Field-p og ammable ga e a a (FPGA ) a e of en ili ed in pace a ionic . To p o ec he FPGA logic again he ioni ing adia ion effec in pace, ed ndanc in fo m of conc en e o de ec ion can be ed.
In hi o k, e p e en a compa a i e d of a pa i -ba ed e o de ec ion i h of a e-ba ed e , and a iple mod la ed ndanc echniq e on a kno n ¯a h-ba ed FPGA a chi ec e (Mi- c o emi P oASIC ). We compa e c i ical pa h dela , ci c i a ea o e head, m l iple bi e o p ob- abili and e o co ec ion ime penal . O anal i ho ha a ol ion ba ed on pa i -ba ed e o -de ec ion can a lea a e abo half of he e o ce o e head ca ed b iplica ion of he
¯ip-¯op if he a ge ci c i can be f nc ionall i ola ed f om he e of he ci c i in he FPGA and if he of a e ppo e an mi ion of acce eq e .
Ke o d :fa l ole ance, FPGA, P oASIC
1 In od c ion
Field-p og ammable ga e a a (FPGA ) a e of en ili ed in pace a ionic d e o hei p oce ing ef®cienc , ep og ammabili , and e en ible in e face capabili ie p o iding
¯e ibili fo a ange of mi ion eq i emen . The a ionic m be p o ec ed f om ion- i ing adia ion in pace. In he ab ence of a hield (e.g., magne ic ®eld of he ea h), a high ene g pa icle can a e e h o gh a digi al ci c i and ind ce igni®can amo n of cha ge, hich can e en all ca e ne pec ed em e pon e like andom ignal gli che on he en o da a, b al o ca a ophic em fail e like mi ion-lo d e o a non e pon i e a elli e [Pe11a]. D e o he lack of co -ef®cien ph ical acce o he pace em, he a ionic m implemen in in ic fa l - ole ance mechani m ba ed on he mi ion eq i emen .
A local co p ion of info ma ion o ed in a node b a ingle ene ge ic pa icle i called ingle e en p e (SEU). If an SEU i la ched b an FF (¯ip-¯op), hen i can e l in a a ic bi ¯ip. The e e o a e no pe manen and can be co ec ed e.g., i h a e e , h he a e al o called of e o [Pe11b]. Sof e o of en happen in he eq en ial elemen of a ci c i , d e o he la ching- indo , elec ical- and logical-ba ie of com- bina o ic [Li94].
1Uni e i of B emen, Reliable Embedded S em , 8 59 B emen, goekce@c . ni-b emen.de Ge man Ae o pace Cen e , In i e of Space S em , 8 59 B emen, goe ch in.fe @dl .de
1415
E o de ec ion in ol e onl he di co e of an e o , hile he e o co ec ion ake ca e of bo h de ec ing and eco e ing he co ec info ma ion af e an p e . Thi eq i e a o of info ma ion ed ndanc in fo m of pace, e.g., iplica ion and o ing, o ime, e.g., p oce ing info ma ion h ee ime b a ingle ni and compa ing he e l . Of en, e o co ec ion in an FPGA i implemen ed i h pace ed ndanc , e peciall a iple mod la ed ndanc (TMR). E o co ec ion picall eq i e mo e e o ce compa ed o e o de ec ion, in fo m of ed ndanc . In p e ence of igh con ain , hi o e head can n in o a h dle fo f l®lling he de ign iming clo e and a ea eq i emen .
OBDH S b em
P oce o link FPGA link S b em
Fig. 1: O e ie of an e ample da a handling em. The p oce o n he mi ion of a e and he FPGA implemen in e face p o ocol ci c i eq i ed b a io b em on-boa d of a
a elli e. The p oce o e he FPGA fo comm nica ing i h he b em .
Al e na i el , a pa of he pace ed ndanc in he FPGA ma be elimina ed b imple- men ing addi ional ime ed ndanc , e.g., in of a e, if he FPGA ac a a co- ni be ide an al ead adia ion-ha dened p oce o . An e ample a chi ec e i depic ed in Fig. 1, he e he FPGA implemen he comm nica ion p o ocol in e face needed fo comm - nica ing i h he a elli e b em and he p oce o n he mi ion of a e. The p oce o e he FPGA in a ma e - la e manne . The FPGA ci c i onl implemen e - o de ec ion and, in ca e of an e o , he of a e in c he FPGA o ep oce he la eq e . Wi h hi collabo a i e app oach, e o co ec ion i achie ed and he o e head of local e o co ec ion i elimina ed. Thi echniq e ill be efe ed a e o de ec ion i h of a e-ba ed e (EDSR). In hi pape , apa i -ba ede o de ec ion echniq e i ed in he implemen a ion of EDSR.
Pa i -ba ed code and iplica iona e ell-kno nconc en e o de ec ion echniq e (CED) [NZ98],[GÈo 8]. Al oe o de ec ion i h e fo achie ing e o co ec ion a p opo ed, e.g., in [Ni99]. In ecen ea , one he one hand, pa ial ha dening echniq e e e p opo ed d e o he ela i el high o e head of CED echniq e , hich elec i el ha den cep ible pa of he ci c i [MT ]. On he o he hand, of a e-ba ed fa l -
ole ance echniq e a e al o pop la d e o he ¯e ibili and ela i el loo e con ain of of a e, e.g., ega ding memo eq i emen , compa ed o ha d a e [Re ],[Go ].
Sof a e- and ha d a e-ba ed echniq e ha e hei adeoff , he efo e he e can al o be ed oge he [Re ].
Thi o k applie pa i -ba ed e o de ec ion i h of a e-ba ed e and iplica ion on an e ample da a handling a chi ec e ba ed on a comme ciall -a ailable ¯a h-ba ed FPGA and p o ide an anal ical compa i on of c i ical pa h o e head, a ea o e head, m l iple bi e o p obabili , and e o co ec ion ime penal . Thi FPGA i cho en be- ca e i i a e-of- he-a fo pace mi ion (e.g., [T 14]) and i i op ionall a ailable in a pecial in eg a ed ci c i package fo pace en i onmen . O con ib ion a e (a) he
di c ion of pa i -ba ed e o de ec ion in he con e of he f ll em ack and (b) he anal i of TMR e EDSR i h e pec o pace-p o en echnolog .
In he follo ing ec ion , e ® l e plain he TMR and EDSR echniq e and he pa - ic la implemen a ion hich a e compa ed. Then, a efe ence da a p oce ing em i p e en ed, hich i ed a a e bench fo compa ing he o implemen a ion . Af e - a d , he anal ical anal i and i e l ba ed on a comme ciall -a ailable ¯a h-ba ed FPGA a chi ec e a e p e en ed. O anal i ho ha he of a e-ba ed e o co ec- ion app oach can c do n a ea o e head abo 5 % compa ed o TMR a he e pen e of e a of a e n ime, if he a ge ci c i can be f nc ionall i ola ed f om he e of
he FPGA ci c i in ca e of an SEU.
Compa ed Ha dening Techniq e
In hi ec ion TMR and EDSR echniq e a e de c ibed mo e in de ail incl ding hei em impac .
.1 T iple Mod la Red ndanc
In TMR, one mod le i iplica ed and he o p of he h ee mod le a e inp o a o e , hich o p he majo i al e. Amod lein hi en e can be an hing f om a hole em o a mall f nc ional block o impl a ga e. TMR ega ding FPGA can be implemen ed a a io ab ac ion le el , e.g., a ci c i - o ga e-le el.
The e a e a io TMR echniq e ba ed on he eliabili eq i emen of a ci c i [Be 8].
One of hem i heLocal TMR(LTMR) and i applied on he ga e le el a combina ional ne being egi e ed b an FF i connec ed o o addi ional FF and he o p of he h ee FF a e connec ed o a majo i o e . In hi o k, onl SEU on he FF a e con ide ed.
Con eq en l , he local TMR i ed a he compa ed TMR echniq e.
TMR de ec and co ec a ingle bi e o on an FF locall ing a majo i o e , hence he TMR echniq e can be a oma icall applied on op of a ci c i . Thi make TMR f nc ionall an pa en o he e of he em, con eq en l he ci c i mo l doe no
eq i e a ede ign befo e mapping o an FPGA.
. E o De ec ion i h Sof a e-ba ed Re
De ec ion of an e o al o eq i e pace o ime ed ndanc , b of en le ed ndanc e o ce han bo h de ec ion and co ec ion. If he e o ce on a de ice a e ca ce and co l , hen implemen ing a local e o co ec ion cheme can become a h dle. In hi ca e, he e o co ec ion can be mo ed, e.g., o of a e, if he p oce ing a chi ec e
ende i po ible. I ing a non-local e o co ec ion eq i e mo e eco e ime han 141
a local co ec ion, beginning f om he de ec ion n il he co ec ion of he e o . Ne e - hele , if he e o a e of he em i lo , hen a non-local e o co ec ion can be p ac icable.
A ell-kno n e o de ec ion echniq e i pa i -ba ed e o de ec ion(PBED), hich add a pa i bi o e e da a o d being o ed, e.g., b XORing he da a bi and o ing he e l along i h he da a o d. [NZ98] Upon eading he da a o d, he pa i i calc la ed again, compa ed o he o ed pa i al e and in ca e of a mi ma ch, an e o ignal i a e ed. S b eq en l , an e o handle can eac and ini ia e a eco e cheme o co ec he e o .
Af e an e o , a mod le m be eco e ed o an ope a ional a e. Of en, hi i done b e e ing he mod le o i ini ial a e. Thi in n lead o a lo of he p oce ing con e ha m be b o gh back, hich in ol e pe iodicall backing p he p oce ing con e , i.e., checkpoin ing. If he p oce ing con e doe no con ain an info ma ion hich i needed fo a long ime, i.e., hen a mod le eg la l fall back o a de®ned a e, hen
he o e head of checkpoin ing in he ci c i ma be elimina ed b ei ing a p oce ing eq e . E ample fo ch a mod le a e a p o ocol con e e o impl a mod le hich e change da a be een o mod le af e efo ma ing da a. The e mod le do no ha e o o e an info ma ion fo a long ime and ha e a de®ned a e af e a ch nk of da a o a an ac ion i p oce ed. The e ample FPGA ci c i B p e en ed in Fig. fall al o in hi ca ego , a i onl e change da a be een o mod le and mo e o i ini ial a e af e a eq e i p oce ed. If an SEU occ d ing p oce ing of a eq e , hen he e o handle can e e he p oce ing mod le and ¯ag an e o o he p oce o ha a p oce ing eq e can be ei ed, i.e., of a e-ba ed e . Al e na i el , in ead of
¯agging, he eq e can be ei ed af e a non e pon i e imeo . In hi ca e, he ime penal ca ed b an SEU i negligible, if he FPGA SEU a e d ing a mi ion d e o
pace adia ion a e lo .
Refe ence A chi ec e
We compa e he o ha dening echniq e ing a efe ence model of an on-boa d da a handling ni fo a a elli e [T 14]. In he follo ing, impo an pa of he em a e de c ibed a he f nc ional le el.
.1 O e ie
The on-boa d da a handling ni comp i e of o main p oce ing mod le : a p oce - o and an FPGA. The p oce o n he mi ion of a e, hich in ol e comm nica - ing i h diffe en b em on-boa d of he pace em. The comm nica ion i done
h o gh he FPGA, hich ac a an in e face componen and implemen he a io comm nica ion in e face needed b he b em (e.g., RS , CAN). Fig. 1 ho an o e ie of he a chi ec e. We a me ha he p oce o , he comm nica ion line be- een he p oce o and he FPGA, and he b em a e f®cien l p o ec ed f om an
FIFO
FIFO Reliable
Ci c i (A)
Un eliable Ci c i
(B) Mem.
Reliable Ci c i
(C) da a
ead en.
da a i e en.
add e da a da a ead en.
i e en.
Fig. : Simpli®ed model of he FPGA de ign a chi ec e. The ci c i in he middle p oce e he memo acce eq e f om he lef ide and e pond acco ding o he e l of he p oce ed e- q e . The eliable pa a e a med o be imm ne o SEU . The n eliable ci c i m be ha dened on he de ign le el.
ingle p e h o gh in in ic ed ndanc in IC and e o -co ec ing code on comm ni- ca ion link .
. FPGA De ign
F om he p oce o poin of ie , he FPGA i a emo e memo b , he e he imple- men ed link in e face a e memo -mapped. The p oce o ili e he e in e face mod le b eading and i ing he e pec i e memo a ea .
The FPGA model con i of h ee f nc ional block , ci c i A, B, and C a ho n in Fig. . Ci c i A e e he memo acce eq e f om he p oce o o ci c i B, hich i e memo acce e on ci c i C and ®nall e n he da a o he p oce o ing he FIFO in e face of ci c i A. Ci c i C i h a memo block in ide e emble he memo -mapped in e face . Reliable ci c i A and C in hi a chi ec e a e a med
o be f®cien l p o ec ed again SEU (e.g., b TMR), he ea he n eliable one m be p o ec ed b a of e o ha dening echniq e. The compa ed ha dening echniq e ill be applied on he n eliable ci c i .
The FIFO and he memo need a ingle clock c cle fo eading o i ing a ingle o d, hich ende he ma king of a ingle o d acce ope a ion in a clock c cle (in ca e of an e o ) po ible.
. Comm nica ion P o ocol
The comm nica ion p o ocol be een he p oce o and he FPGA con i of o kind of me age : eq e and e pon e. The p oce o end memo acce eq e fo a pe- ci®c add e o add e in e al o he FPGA and he FPGA e pond i h he acco ding e pon e: In ca e of a ead eq e , he e pon e ca ie he da a hich i eq e ed b he p oce o . If a i e eq e i i ed, he FPGA end an ackno ledge (ACK) e pon e af e he i e eq e i comple e. A no -ackno ledge (NACK) e pon e i en , if a e- q e canno be cce f ll p oce ed. E e eq e i an e ed i h a e pon e and a
econd eq e canno be en befo e he e pon e o he ® eq e ha been ecei ed.
1419
FIFO
FIFO Reliable
Ci c i (A)
Un eliable Ci c i
(B)
E o De ec ion
E o Handling
Mem.
Reliable Ci c i
(C)
e o da aead en.
o p en.
da ai e en.
add e da a da a ead en.
i e en.
o p en.
e e
Fig. : Pa i -ba ed e o de ec ion applied on he n eliable ci c i . Da a ed ndanc i gene a ed b he pa i gene a ion block. The e o de ec ion block check he da a in eg i . The e o handling block gene a e he eco e and ma king ignal . The AND ga e i ola e he n eliable ci c i b ma king all he con ol ignal hich can change he a e of he neighbo ci c i .
4 Implemen a ion
Thi ec ion e plain ho he pa ic la TMR and EDSR ing PBED echniq e a e implemen ed on he efe ence a chi ec e.
4.1 T iple Mod la Red ndanc
In hi o k, e concen a e on he SEU in he eq en ial pa of a ci c i , he efo e LTMR i implemen ed a he compa ed TMR echniq e. The implemen a ion i aigh - fo a d and i doe no eq i e addi ional a en ion on he ha dened ci c i , beca e i can be applied on op of a logical ci c i befo e i i placed and o ed fo he FPGA.
4. E o De ec ion i h Sof a e-ba ed Re
Fig. ho PBED applied on he efe ence FPGA de ign. The e o de ec ion block con in o l gene a e he da a ed ndanc and check he in eg i of da a. If an e o i de ec ed, hee o ignal i a e ed and hee o handlingblock immedia el ma k he con ol ignal on ei he ide of he n eliable ci c i .
The FF in he n eliable ci c i a e egmen ed o g o p and fo each g o p one pa i FF i in od ced. One ingle g o p i h a pa i FF i called acl e. Fig. 4 ho he gene ic implemen a ion of he e o de ec ion in a ingle cl e . The n mbe of cl e i gi en b ccl(c: co n , cl: cl e ). Each cl e con ain cl−1 e FF pl one pa i FF ( : i e). E en pa i i gene a ed b XORing he inp o he e FF b he XORpg. The in eg i of he o ed bi i checked b he XORpc i h cl inp and hecl e e o i gene a ed b each cl e . Finall ,cclcl e e o ignal a e ed ced o a ingle
Comb.
Logic FF Comb.
Logic
XORpg (pa i gene a ion)
FF
XORpc (pa i check)
cl e e o
cl−1 cl−1
FF cl e (#FF = cl)
c i,PBED,1 c i,PBED,
Fig. 4: Implemen a ion of PBED pa (a): gene a ion of he cl e e o ignal.
FF cl e
ORdc ( ed c ion)
e e
o p en.
con ol ignal
ma ked con ol ignal ccl
e o
c i,PBED,
Fig. 5: Implemen a ion of PBED pa (b): gene a ion of he global e o ignal and e o handling.
e o ignal b an OR ga e. The ed c ion of he cl e e o ignal and b eq en e o handling i ho n in Fig. 5.
The e o handling i done b gene a ing he e e ando p enable ignal combina- ionall ing he e o ignal. The enable ignal ma k he con ol ignal (i.e., FIFO and memo con ol ignal ) of he n eliable ci c i . The e e ignal eco e he ci c i f om a po ibl e oneo a e o i ini ial a e. In he ne c cle, he e o ¯ag i dea e ed and he n eliable mod le begin da a p oce ing again.
If an incomple e o no e pon e i ecei ed b he p oce o in he imeo indo , hen a eco e p oced e i ini ia ed. If an e o happen d ing p oce ing of a ead eq e , hen hi eq e i epea ed. If an e o occ in he middle of a i e an ac ion, he of a e canno kno hich pa of he an ac ion a comple ed and he of a e can nch oni e i elf b eading he e add e e again o impl e he la an ac ion.
If a i e o a memo loca ion igge an ope a ion (e.g., an mi ing a command o a b em), hen e ing e igge he la ope a ion, hich can be nde i able and dange o .
In ca e of chac ion- igge ingmemo loca ion , he of a e can i e ingle memo i e ope a ion onl . Thi ha he ad an age ha e e a omic memo i e ope a ion i ackno ledged epa a el and he of a e kno e ac l hich ingle memo ope a ion did no cceed. Thi eq i emen can be loo ened, if a memo a ea i i en hich doe no igge an ac ion, i.e., he o p of he a ge em doe no change af e he
14 1
an ac ion. An e ample i he an mi b ffe of a comm nica ion in e face mod le, he e he an mi ope a ion m be ® igge ed b e ing a bi in a con ol egi e allo ing o begin a da a an fe o a b em. In hi ca e, he p oce o o ld ® o i e he an mi pa load-da a o he b ffe i h a ingle i e eq e and in he b eq en eq e he an mi ion ope a ion o ld be igge ed ing an a omic memo acce .
5 Anal ical Compa i on of Needed Re o ce
In hi ec ion, e anal icall de e mine and compa e c i ical pa h dela , ci c i a ea o e head, m l iple bi e o p obabili and di c he e o co ec ion ime penal of he o ho n echniq e . The ci c i a e mapped o he Mic o emi ¯a h-ba ed adia ion- ole an P oASIC FPGA (RT PE) [Mic1 ] fea ing h ee inp LUT . Thi i a kno n
pace-p o en FPGA and ili ed in a e-of- he-a on-boa d-comp ing em .
Man of he compa i on pa ame e a e dependen on he i e of one cl e cland he o al cl e co n in he n eliable ci c i ccl. The pa ame e a e de e mined fo cl !
= andccl !
= , he e , 2N, hich ® he RT PE a chi ec e i h h ee inp LUT . Thi elec ion of inp pa ame e make he mo iming-ef®cien e of he FPGA a ea fo a peci®c logic dep h. Wi h he inc ea ing co n of clandcclmo e LUT a e needed fo pa i gene a ion and he ed c ion of cl e e o ignal , e pec i el . Wi h inc ea ing n mbe of LUT on a c i ical pa h, longe dela i in od ced on hi pa h. Ho e e , he addi ional dela i onl p opo ional o he loga i hm of cl andccl. Con eq en l , he c i ical pa h of a benchma k de ign onl change fo diffe en al e , 2N, leading o ch elec ion of clandccl al e . Thi beha io i i ali ed in Fig. and e plained in S b ec ion 5.1 mo e in de ail.
In PBED, fo each g o p of cl−1 FF one pa i bi i gene a ed. Logic op imi a ion (e.g., logic packing, e iming) and in e connec dela a e no con ide ed, hich depend
igni®can l on he e o ce ili a ion in an FPGA.
In he follo ing, he nominal pa ame e (i.e., ha dening no implemen ed) a e labeled i h he b c ip nomand he pa ame e of he ci c i i h LTMR and PBED i hLTMR
andPBED, e pec i el . An o e head in a mea emen pa ame e b he applied echniq e i labeled i h he b c ip +.
5.1 C i ical Pa h Dela
The c i ical pa h dela c i limi he ma im m f eq enc of a de ign and inc ea e i h addi ional e ial logic. In LTMR, e e bi m be decoded b a majo i o e (MAJ ) befo e i i p opaga ed o he combina ional logic, hich ca e an e a dela . The b-
c ip pd and fo p opaga ion dela .
c i+,LTMR= pd,MAJ (1)
In PBED, he e a e o c i ical pa h candida e ( ee Fig. 4 and 5):
1. The c i ical pa h of he nominal ci c i pl he pa i gene a ion pa h (c i,PBED,1) . The e o de ec ion pl he e o handling pl he i ola ion pa h (c i,PBED, )
The ® pa h dela can be calc la ed a follo : The pa i ha o be gene a ed befo e he combina ional ignal a e egi e ed. The p opaga ion dela of he XORpgblock i called
pd,XORpg.
c i+,PBED,1= pd,XORpg ( ) The e o de ec ion pa h con i of he XORpc, ORdc, a NOT ga e, and an AND ga e (Fig. 4 and 5). The NOT ga e and he AND ga e can be packed in o one LUT, hich i calledOR A:
c i,PBED, = pd,XORpc+pd,ORdc+pd,OR A ( )
XORpc, XORpgand ORdc a e ee of LUT a ho n in Fig. . The p opaga ion dela of a block i h an inp i e inp i called pd(block, inp ) and can be calc la ed b de e mining he dep hd of he ee and m l ipl ing i i h he p opaga ion dela of he
e pec i e h ee inp mac o (e.g., OR fo an OR block), a he in e connec dela a e no con ide ed.
pd(block, inp ) =dblock· pd,mac o
= log inp · pd,mac o (4)
n
LUT
LUT LUT
LUT LUT
LUT LUT
dep h 1 . . . d−1 d
1 ...
... n
Fig. : The ®g e ho ho a ga e i hninp i mapped o an FPGA a chi ec e i h h ee inp LUT . Af e mapping, a LUT ee i h a dep h ofd= log n i c ea ed. No e ha ifni no a po e of h ee, hen no all he leaf of he ee e i .
14
Wi h Eq. 4, he p opaga ion dela of he h ee de®ned block can be calc la ed:
pd,XORpg= log ( cl−1) · pd,XOR pd,XORpc= log cl · pd,XOR
pd,ORdc= log ccl · pd,OR
=?
log ?cFF,nom cl
CC· pd,OR
(5)
A c i,PBED, i gene a ed in pa allel o he nominal ci c i (i.e., no e ial like c i,PBED,1),
c i,PBED, a nc i ical p o a ce ain dep h of pa i check and ed c ion block . The e-
fo e he pa ame e clandcFF,nomlimi he ma im m f eq enc of he de ign.
A a j nc ion empe a e of 1 5°Cand o -ca e ppl ol age 1.14 V, he pd,MAJ ,
pd,XOR , pd,OR , pd,OR A a e 1.14 n , 1.4 n , 1 n and 1 n e pec i el [Mic1 ]. Wi h he e da a he c i ical pa h ca ed b he FF and combina ional elemen can be calc la ed fo a io clandcFF,nompa ame e .
c i+,1(n ) c i, (n ) A ea+ A ea+:cFF,nom
( , ) cl cFF,nom PBED LTMR PBED PBED LTMR PBED LTMR
(1,4) 1
1.4 1.14
.84 48 48 15 %
(1,5) 48 8.84 4 1458 151 % %
(1, ) 1458 9.84 19 4 4 15 %
( , ) 9
1
.84 1.14
8. 51 48 114 %
( ,4) 48 9. 1944 114 % %
( ,5) 1944 1 . 195 58 11 %
( , ) 4
4. 1.14
8. 8 111 %
%
( , ) 9. 8 4 1 1 %
( ,4) 1 1 . 8 4 18 1 5 %
Tab. 1: Compa i on of PBED and LTMR ega ding c i ical pa h and a ea o e head.
Table 1 ho he c i ical pa h dela c i+,1 and c i, fo a io al e of he inp pa ame e ( , ). The pa ame e clandcFF,noma e de e mined ing( , ), he e cl= , cl e co n ccl= and nominal FF co n cFF,nom= (cl−1)·ccl. Wi h inc ea ing dep h of XORpg, c i+,1 g o fo PBED, i.e., e e ime hen cl eache a highe po e of . The addi ional pa h dela c i+,1of LTMR i independen of he inp pa ame e . Fo
cl= PBED and LTMR ha e a imila c i ical pa h o e head. PBED ha addi ionall he
c i+, , hich g o i h inc ea ing dep h of XORpcand ORdcblock .
pd,OR and pd,OR A e e a ailable nei he in he da a hee o mac o lib a doc men a ion. The efo e an e i- ma ed al e of 1 n i a med fo he e o pa ame e .
5. Ci c i A ea O e head
A ming ha he ci c i a ea i p opo ional o he CLB co n , e de®ne he pa ame e A eaa he CLB co n . Fo compa i on, e a e in e e ed in he a ea o e headA ea+, i.e.,
he CLB co cCLB+:
A ea+=cCLB+ ( )
In P oASIC a chi ec e, e e con®g able logic block(CLB)4can be ei he con®g ed a an FF o LUT. Then, he ci c i a ea o e head can be calc la ed b adding he co n of addi ionall in od ced LUT and FF :
cCLB+=cLUT++cFF+ ( )
In he LTMR de ign, he FF a e iplica ed, i.e., o addi ional FF a e added fo each FF:
cFF+,LTMR= ·cFF,nom (8)
LTMR eq i e one LUT pe FF a o e :
cLUT+,LTMR=cFF,nom (9)
In o al, he a ea o e head fo LTMR i :
A ea+,LTMR=cCLB+,LTMR= ·cFF,nom (1 ) In PBED, one pa i egi e i needed fo a ingle cl e :
cFF+,PBED=ccl (11)
In PBED, LUT a e needed fo he XORpg-, XORpc-, ORdc-block , and OR A ga e fo ma king he con ol ignal :
cLUT+,PBED=ccl(cLUT,XORpg+cLUT,XORpc)
+cLUT,ORdc+cLUT,OR A (1 )
A ho n in Fig. , a block i hninp blocknc ea e a ee, o he needed ma im m LUT co n fo a ee of dep hd can be de e mined b he follo ing fo m la, a ming
ha e e ne le el of he ee in od ce dep hLUT a ma im m:
cLUT,blockn,ma =
dblockn−1 i=
Â
i
=1
·( dblockn−1)
(1 )
4In P oASIC e minolog , a CLB i called a ileo Ve aTile
14 5
U ing he fo m la fo dep hd= log n (Fig. ):
cLUT,blockn,ma =1
·( log n −1) (14) Ifni a po e of (e.g., in ca e of XORpc and ORdc), hen he eq a ion can be f he
impli®ed:
n=! , 2N =) log n =n
=) cLUT,blockn=1
·(n−1) (15) Ifn+1 i a po e of (e.g., in ca e of XORpg), he ame amo n of LUT a e eq i ed.
Thi i d e o he fac ha a block ill in hi ca e con ain a ingle o-inp LUT i h he e being h ee-inp LUT . A o- and a h ee-inp LUT bo h occ p one CLB, h he ame a ea.
n+1=! , 2N =) log n =n+1
=) cLUT,blockn=1
·n (1 )
Wi h Eq. 15,cLUT,XORpc andcLUT,ORdc and i h Eq. 1 ,cLUT,ORpg can be de e mined.
Addi ionall , he e a e fo OR A in he PBED implemen a ion. Hence, he Eq. 1 can be e i en o:
cLUT+,PBED=
=ccl
d1
·(cl−1) +1
·( cl−1)k +1
(ccl−1) +4
=ccl( cl−1) +1
(ccl−1) +4
(1 )
Finall , i h Eq. , 11 and 1 , o al a ea co fo PBED eq al o:
A ea+,PBED=ccl+ccl( cl−1) +1
(ccl−1) +4
=ccl( cl+1 ) + .5
(18)
cFF,nomi a main inp pa ame e , he efo e i i be e o e i eccl ingcFF,nom: A ea+,PBED=cFF,nom
cl−1( cl+1
) + .5 (19)
Table 1 ho he a ea o e headA ea+and a ea o e head ca ed pe FFA ea+:cFF,nom5
fo a io al e of cl andcFF,nom pa ame e . PBED a ea o e head i app o ima el 59 % of he LTMR a ea o e head fo cl= and i dec ea e i h inc ea ing clandccl. The LTMR a ea o e head i independen of he inp pa ame e .
5A ea o e headA ea+i ela ed ocFF,nomin ead of he hole de ign incl ding combina o ic , beca e he a ea o e head i onl dependen oncFF,nomand he combina o ic LUT co n i a bi a .
5. M l iple bi e o p obabili
We appl he de®ni ion of a cl e al o on LTMR and de®ne an LTMR cl e a he g o p of h ee FF af e iplica ion, i.e., cl e,LTMR= . LTMR and PBED echniq e bo h a e imm ne again one bi ¯ip in a clock c cle, b no again m l iple bi e o , a ming ha e e FF in LTMR i pda ed in e e clock c cle . In hi b ec ion, e ill compa e he LTMR and PBED ega ding m l iple bi e o p obabili , i.e., he p obabili ha an e o canno be de ec ed on he ci c i .
If a ingle pa icle a el h o gh he ci c i , hen i can ca e ingle o m l iple bi e o dependen on he amo n of ene g an fe ed o he ci c i and he i e of he IC c-
e . In hi anal i , e a me ha he CLB a e fa eno gh f om each o he o con ide bi ¯ip a independen e en . The efo e, de®nepa he bi ¯ip p obabili of a ingle FF in a clock c cle and a me ha pfo indi id al FF a e a i icall independen . Then, he m l iple bi e o (MBE) p obabili in a ingle cl e pMBE,clcan be calc la ed b :
pMBE,cl=
Â
cli=
g cl
i n
pi(1−p)cl−i
=1−
Â
1 i=g cl
i n
pi(1−p)cl−i
=1−(1−p)cl− cl·p(1−p)cl−1
( )
The la eq a ion a me ha all kind of m l iple bi ¯ip canno be de ec ed b PBED.
In fac , PBED can de ec all odd n mbe of bi ¯ip in a cl e , b he p obabili of m l iple bi ¯ip in a cl e g ea e han i negligible. Wi hpMBE,cl, he m l iple e o p obabili of he hole ci c i pMBE can be calc la ed in a imila manne like in he p e io eq a ion:
pMBE=
ccl i=1
Â
gccl
i n
piMBE,cl(1−pMBE,cl)ccl−i
=1−(1−pMBE,cl)ccl
=1−((1−p)cl+ cl·p(1−p)cl−1)ccl
( 1)
A ming one ea mi ion in L o bi nde 1 cm hielding, a p og ammed ci c i i h 5 FF on an RTPE L FPGA ha fo SEU [BSV11]. If hi de ign n a MH ,
henpcan be calc la ed b :
p=4/5 / 5/ 4/ / /( ⇥1 )
⇡1. ⇥1 −18 ( )
Table ho a compa i on of m l iple bi e o p obabili ie fo a io clcFF,nompa- ame e . Fo cl= ,pMBEi app o ima el he ame fo PBED and LTMR. Gene all ,
O he i e, he bi ¯ip can acc m la e and lead o nco ec able e o .
14
hencFF,nominc ea e ,pMBEal o inc ea e , b fo cl> , PBED i mo e cep ible o m l iple bi e o .
pMBE ( , ) cl cFF,nom PBED LTMR
(1,4) 1 .8 E- 4 .8 E- 4
(1,5) 48 . 5 E- . 5 E-
(1, ) 1458 . 4 E- . 4 E-
( , ) 9
1 1. 5 E- 1. 4 E-
( ,4) 48 . 5 E- .1 E-
( ,5) 1944 1.1 E- 1 9. 8 E-
( , ) 4 1. E- 1 1.1 E-
( , ) .9 E- 1 . 9 E-
( ,4) 1 1.19 E- 1. E-
Tab. : Compa i on of PBED and LTMR ega ding m l iple bi e o p obabili of one cl e pMBE,cland hole ci c i pMBE
O e all, cl= i a ea onable choice fo a ing igni®can amo n of FPGA e o ce , and fo ha ing a li le impac on he c i ical pa h a po ible. If he ma im m f eq enc i no impo an , hen highe cl e l in le a ea o e head p o app o ima el 5 % of
he LTMR a ea o e head.
5.4 E o Co ec ion Time Penal
In LTMR, he e o i co ec ed in he ame clock c cle, b EDSR eq i e ha he e - o i co ec ed b he of a e b epea ing he memo acce eq e , hich in n ca e addi ional p oce ing dela . Con eq en l , he o al ime penal i p opo ional o he e o a e d ing he mi ion. Fo e ample, a ming he ame e o a e f om he Sec ion 5. make he ime penal pe ea in igni®can .
Concl ion
The FPGA ed in pace applica ion m be p o ec ed again adia ion ind ced e o , hich i of en done b ed ndanc . TMR i of en ed on FPGA de ign , hich can co - ec he ind ced e o locall . If he logic e o ce a e ca ce and SEU a e on he FPGA d ing a mi ion i lo , hen he e o co ec ion f nc ionali can be hif ed o he of - a e, lea ing an FPGA ci c i onl i h e o de ec ion. We ha e ho n an e ample a - chi ec e hich implemen PBED i h of a e-ba ed e and anal icall compa ed he needed e o ce fo he Mic o emi P oASIC a chi ec e. The e l ho ha ig- ni®can pa of he a ea o e head ca ed b he LTMR can be a ed b implemen ing PBED on an FPGA ci c i and co ec ing he e o i h ime ed ndanc , i.e., epea ing
he in c ion o he FPGA in ca e of an e o . The di ad an age of PBED ho p fo g ea e cl al e hen he c i ical pa h fo pa i gene a ion g o . Ne e hele , if he ma im m f eq enc i no he ® p io i in de ign, hen igni®can a ea can be a ed a a co of highe pMBE. In ce ain applica ion hi ma be he ke o adop f®cien f nc ionali in a ingle FPGA componen .
Ackno ledgmen
Thi o k ha been ppo ed b he Uni e i of B emen G ad a e School S De, f nded b he Ge man E cellence Ini ia i e.
Refe ence
[Be 8] Be g, Melanie: De ign fo Radia ion Effec . P e en a ion f om Mili a and Ae o pace P og ammable Logic De ice (MAPLD) Wo k hop, 8.
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[Go ] Golo be a, Olga Reba dengo, Ma i io Reo da, Ma eo Son a Violan e, Ma imo:
Sof a e-implemen ed ha d a e fa l ole ance. Sp inge , .
[GÈo 8] GÈo el, Michael Oche e n , Vi al Sogomon an, Ego Ma ienfeld, Daniel: Ne me h- od of conc en checking, ol me 4 of F on ie In Elec onic Te ing. Sp inge Ne he land , 8.
[Li94] Liden, P. Dahlg en, P. Johan on, R. Ka l on, J.: On la ching p obabili of pa icle ind ced an ien in combina ional ne o k . In: 4 h In e na ional S mpo i m on Fa l - Tole an Comp ing (FTCS). pp. 4 ± 49, J ne 1994.
[Mic1 ] Mic o emi. Radia ion-Tole an P oASIC Lo Po e Space¯igh Fla h FPGA Da a hee , No embe 1 .
[MT ] Mohan am, K. To ba, N.A.: Co -effec i e app oach fo ed cing of e o fail e a e in logic ci c i . In: In e na ional Te Confe ence (ITC). ol me 1, pp. 89 ±9 1, Sep
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[Ni99] Nicolaidi , M.: Time ed ndanc ba ed of -e o ole ance o e c e nanome e echnolo- gie . In: 1 h IEEE VLSI Te S mpo i m. pp. 8 ±94, 1999.
[NZ98] Nicolaidi , M. Zo ian, Y.: On-Line Te ing fo VLSI - A Compendi m of App oache . Jo nal of Elec onic Te ing Theo and Applica ion (JETTA), 1 : ± , Feb a 1998.
[Pe11a] Pe e en, Ed a d: Single E en Effec in Ae o pace. John Wile & Son , chap e 1, 11.
[Pe11b] Pe e en, Ed a d: Single E en Effec in Ae o pace. John Wile & Son , chap e , 11.
[Re ] Reba dengo, M. Reo da, M.S. Violan e, M. Nicole c , B. Vela co, R.: Coping i h SEU SET in mic op oce o b mean of lo -co ol ion : a compa i on d . IEEE T an ac ion on N clea Science, 49( ):1491±1495, J n .
[T 14] T e dle , Ca l Johann Sch Èode , Jan-Ca en G eif, Fabian S ohlmann, Kai A do , GÈokcËe Fe , GÈo ch in: Scalabili of a Ba e Le el De ign fo an On-Boa d-Comp e fo Scien i®c Mi ion . In: P oceeding of he Da a S em in Ae o pace (DASIA) Con- fe ence. 14.
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