MAINTENANCE MANUAL

(1)

MAINTENANCE MANUAL VOLUME IT

-

DIGITAL EQUIPMENT CORPORATION. MAYNARD, MASSACHUSETTS

(2)

LINC-8

MAINTENANCE MANUAL

VOLUME n

November 1967

F-L87

(3)

Copyright 1967 by Digital Equipment Corporation

(4)

Page

- -

ADA i ~ 4

ADD x 4

ADM i ~ 5 BCL i ~ 5 BCO i ~ 6 BSE i ~ 6 DSC i ~ 7 DIS i a 8

JMPx 9

Drawing Number D-BS-LINC8-0-L2 D-BS-LINC8-0-L3 D-BS-LINC8-0-L4 D-BS-LINC8-0-L5 D-BS-LINC8-0-L6 D-BS-LINC8-0-L7 D-MU-UNC8-0-L 10 D-MU-LINC8-0-L 11

VOLUME II

LINC-8 ENGINEERING DRAWINGS

Thisvolume of the LINC-8 Maintenance Manual contains instruction timing-flow diagrams, engineering drawings, and modu Ie schematics not found in other related documents. These drawings cover the basic LINC-8 system de- scribed in Volume I and are I isted below.

Instruction Tim ing-Flow Diagrams Eng ineering Drawings (cont)

Page Page Page Drawing Number Title

LAM i ~ 9 SAM i a 14 SXL iN 19 D-BS-LINC8-0-L 14 Contro I Reg ister and Instruction Decoders LDA i ~ 10 SET i a 15 UMB N 19 D-BS-LINC8-0-L 15 Time Pu I se Di stri butor

LDH i ~ 10 SCR iN 15 XSK i a 20 D-BS-LINC8-0-L 16 LINC Interface Control

LMB N 11 SHD i ~ 16 8 Execute Class 20 D-BS-LINC8-0-L 17 lOT Decoders

MSC N 11 SKP iN 16 MTP D-BS-LINC8-0-L 18 Control Function

MULi~ 12 SRO i ~ 17 OPR D-BS-LINC8-0-L 19 Skip Nets

ROL iN 13 STA i ~ 17 EXC D-BS-LINC8-0-L20 Control Pulse Gates

ROR iN 13 STC x 18 D- BS- LINC8-0-L21 S, P, Z, T, N and Dis. Cont. Pulses

SAE i ~ 14 5TH i ~ 18 D-BS-LINC8-0-L22 A and B Register Control Pulses

D-BS-LINC8-0-L26 Memory Extension Eng ineering Draw ings

D-BS-LINC8-0-L28 LINC Sw itches and Ind icators

Title Rev ision Page D-MU-LINC8-0-M3 LINC-8 UML, MA-MD

B-Reg ister 21 D- MU- L I NC8-0- M4 LINC-8 UML, ME-MJ

5 and P Reg isters 22 D-BS-LINC8-0-M8 PDP-8 ADDR Input Gates

Link, Left Half A-Register 23 D-BS-LINC8-0-M9 Mag Tape Reader/Writer

Right Half A-Register 24 D-BS-UNC8-0-M10 Mag Tape Motion Control

Rand Z Reg isters A 25 D-BS-LINC8-0-M11 Mag Tape Tim ing Generator

PDP-8 AC Input Gates A 26 D-BS-LINC8-0-M12 Mag Tape Mode Con tro I

LINC8, UML, LE-LJ F 27 D-BS-LINC8-0-M13 Mag Tape Mark Wi ndow

LINC8 UML, LA-LD B 28 D- BS-UNC8-0-M 111 Te leprinter

Revision Page 29

A 30

31 A 32

A 33

34 A 35

36 A 37

A 38

39 C 40

D 41

42 43

A 44

A 45

A 46

B 47

C 48

(5)

Eng ineering Drawings (cont) Engineering Drawings (cont)

Drawing Number Title Revision Page Drawing Number Title Revision Page

D-BS-LINC8-0-M112 X-Axis Selection 49 D-FD-LINC8-0-9 Flow Diagram, Manual Operations 75

D-BS-LINC8-0-M113 Y-Axis Selection 50 D-FD-LINC8-0-30 Flow Diagram, Load 76

D-BS-LINC8-0-M115 Sense Amps, Inh ibit Drivers, Mem. Cont. B 51 D-AD-300481 0-0-0 Console Scope Overall (Sheet 1) A 77

D-BS-LINC8-0-M116 In Out Buffers 52 D- AD-300481 0-0-0 Console Scope Inten (MTG Mode) (Sheet 4) A 78

D-MU-LINC8-0-P3 LINC8 UML, PE-P J C 53 D- BS-300481 0-0-1 Display Ampl ifier Intensifier Circu it 79

D-MU-LINC8-0-P4 LINC8 UML, PA-PD C 54 D-BS-3004810-0-2 Console Scope Elec. Mod. 80

D-BS-LINC8-0-P23 Data Bits, 00-11 Gates A 55 D-SC-3404601-0-0 Tape Head 81

D- BS- L I NC8-0- P24 Analog System 56 E-AD-7005114-0-0 Control Panel (2 Sheets) 82,83

D-BS-LINC8-0-P25 MB ^& Load Mods in PDP-8 57 D-AD-7005164-0-0 Power Input Panel Assy. C 84

D- BS-LINC8-0-P27 PDP-8 Switches and Indicators 58 D-IA-7005186-0-0 Scope Cable 85

D-BS-LINC8-0-P102 Accumulator A 59 D-IA-7005187-0-0 LINC Tape Unit Cable 86

D-BS-LINC8-0-P103 AC Control 60 D-UA-7005260-0-0 Tape Transport A 87

D-BS-LINC8-0-P104 PC and MA Registers 61 D-IA-7005423-0-0 LINCtape Extension Cable 88

D-BS-LINC8-0-P105 MB Register and Control A 62 D-AD-7404146-0-0 Tape Chassis (Sheet 1) B 89

D- BS- LI NC8-0- P 1 06 Major States and Instruction Register A 63 D-AD-7404146-0-0 Tape Chassis (Signal Wiring) Sheet 3 B 90

D-BS-LINC8-0-P108 MAl PC Contro I A 64 D-AD-7404146-0-0 Tape Chassis (Signal Wiring) Sheet 4 B 91

D-BS-LINC8-0-PI09 Timing Keys, SWS and Run B 65 D-BS-7404146-0-1 Tape Chassis, Power and Control A 92

D- BS- LI NC8-0- P 1 1 0 Input/Output Control B 66 D-AD-7404150-0-0 Tape Drive (LINC8) 93

D-SD-UNC8-0-1 System Configuration 67 D- BS-7404538-0-1 Scope Plug-In (Component MTG) 94

D- BS-LINC8-0-2 Data Terminal Panel Logic 68 C- IA-7405611-0-0 Cable, Scope (Remote) A 95

D-MU-UNC8-0-3 Data Terminal Panel UML 69 A-MDL-UNC8-0-0 Master Drawing List 96

D- IC-LINC8-0-4 Cables, LINC-8 (Sheet 1) B 70 A-CP-UNC8-0-7 External Component List (Sheet 1) B 96

D- IC-LINC8-0-4 Cables, LINC-8 (Sheet 2) 71 A-CP-LINC8-0-7 External Component List (Sheet 2) 97

D- IC-UNC8-0-5 I/O Listings 72 A-ML-LINC8-0-L Drawing List, LINC Section J 97

D- IC-LINC8-0-6 Cable List B 73 A-ML-LINC8-0-M Drawing List, Memory Sec t i on J 98

D-FD-UNC8-0-9 Flow Diagram, Automatic Operations 74 A-ML-LINC8-0-P Drawing List, Processor Section H 98-

2

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Module Schematics Modu Ie Schematics (cont)

Number Title Revision Page Number Title Rev i sion Page

A 130-0-1 Multiplex LINC-8 A 99 R203-0-1 Triple Flip-Flop 3 104

A202-0-1 Two Analog Preampl ifiers B 99 R204-0-1 Quadruple FI ip-Flop E 105

A401-0-1 Sample and Hold A 99 R302-0-1 Delay P 105

A502-0-1 Difference Ampl ifier D 99 R303-0-1 Integrating One Shot H 105

A601-0-1 3 Bit DAC F 100 R401-0-1 Clock M 105

A604-0-1 2 Bit DAC D 100 R405-0-1 Crystal Clock J ₁₀₆

A704-0-1 -10V Prec ision Power Supply H 100 R601-0-1 Pulse Amplifier P 106

A706-0-1 Power Supply for A202 A 100 R602-0-1 Pu Ise Ampl ifier N 106

B104-0-1 Inverter C 101 R603 Pu I se Ampl ifier 5 106

B115-0-1 Diode Gate C 101 R613-0-1 Pulse Amplifier B 107

Bl17-0-1 Diode Gate B 101 R650-0-1 Bus Driver P 107

B130-0-1 3 Bit Parity Circuit A 101 W002-0-1 Clamp Loads B 107

B171-0-i Diode Gate C 102 \"/005-0-1 Clamped Loads B 107

B204-0-1 Four FI ip-Flops B 102 W026 Connector Board 108

8684 Two Bus Drivers 7 102 W035-0-1 Cable Connector 108

G882 Manchester Reader Writer 102 W050-0-1 Indicator Driver D 108

G906-0-1 LINC8 Capac itor and Power Up 103 W072-0-1 LINC-8 Scope Cable Connector 108

R 112-0-1 NOR Gate A 103 W073-0-1 LINC-8 Tape Cable Connector 109

R 141-0-1 Diode Gate F 103 W500 High Impedance Follower 109

R151 Binary to Octal Decoder 3 103 W501 Schm itt Trigger 4 109

R181-0-1 DC Carry Chain D 104 W607-0-1 Pulse Amplifier F 109

R201-0-1 FI ip-Flop D 104 W640-0-1 Pu Ise Ampl ifier J 110

R202-0-1 Dual FI ip-Flop F 104

3

(7)

PDP-8

1

PROCESSOR

LINC PROCESSOR

I I MD PDP-8 TIMING

IN DATA DIRECTION

OUT

MB REGISTER

---f

SENSE AMPLIFIERS

- - - -

S REGISTER

j

P P REGISTER

B REGISTER

---i

A REGISTER

C REGISTER

---f

MEM-B

-I

FLIP-FLOPS

P+I

Tl MD I

I

~ I

- - - -

~

I

~P+Il

/ I

"'"

I I _I I ^I I I I

\

t

ADAi./3

b

'.;;./

TI MD TI MD

NDX

J I

I

•

^I

- - - - -

~----

-

y* p*

~

I I

*

I...d;;;,.P p*+,

. ' - '

,

Y NDX \

l!h 1 '+'

1 BCOA ^I

I CARRY

J I

LlNC TI MING

_.---.---~-<O:"'I----,-,3~-,----"""T-"""T----

CONDITIONS .i.

ft I

_I

0 0

0 "0

1 0

"0 II ..

y*

y Y P+I I Y+I

GNI GO

P*

P+2 P+' P+2 P+I

. .

II

/

I

Tl

l O - T T1

/

I

_I T2

I

,

T2 P+l-S, P+2-P

ft-S

T3 TIO

I \ Til T LAST

I

\

^GNI ^GO

+

T3

I

TIO B-S B-S

I

Ptl-S, Pt2-P INDEX

e

^!

PDP-8

r

PROCESSOR

LlNC PROCESSOR

4

Tl MD Tl MD

PDP-8 TIMING IN DATA DIRECTION

OUT

MB REGISTER

- - /

_~ ^II

SENSE AMPLIFIERS

- - ---- - - - - - - -

P X

S REGISTER

j ~

P Ptl P REGISTER

B REGISTER

---f

A REGISTER

C REGISTER

- - /

MEM-B FLIP-FLOPS

-I

c

H

I I I I

I

,

ADD X

1

I ' - '

TI MD

r

J

I

- - - - - - -

P +1

"

P + 2

r

• ^r

⁰^tr

BCOA I I CARRY

J

I

LlNC TIMING - r j - - . - - - - . . . . , - - . . . . , . . - - - _ , _ - - , - - - - -

GNI GO TI T2 T3 T LAST

I ,

GNI GO

(8)

T1 MD Tl MD Tl MD

n

MD Tl MD

T1 "0

PDP-8 TIMING ~L-~L-____ ^~__ ^~______ ^~__ ^~______ - L __ - L ______ ~ __ ~ ______ ~ __ ~ ____ _ _

IN DATA DIRECTION PDP-8

PROCESSOR

lINC PROCESSOR

I

CONDITIONS .i. jJ

0 0

0 J60

,

0

,

_"0

OUT ---~

NDX

+

MB REGISTER

~

Î ÎÎ Î

•

^-.IÎ ÎÎ

~

SENSE AMPLIFIERS

--- - - - - - - - - - - - - - --- --- - - --- --- - - - ^{- - - -}

^{- -}

S REGISTER P P REGISTER

B REGISTER

----1

A REGISTER

C

REGISTER ~

MEM-B

-1

FLIP-FLOPS

Ptl

,.. _~

V*

/

~Ptll

^I ^I ^*

I I /l,P

I ^'-"

~

I

V NDX \ I I

I ^I I

I

a

I I

\

I ,

I \

1 AD"'~\@

I P*+I

1 r _...L. o+r _I

1

^I

t

^{, o+r}

BCOA CARRV ^"-'

lINC TI MING

--r--r---r-...::.<TI---,-,3...;;:a--,---,---,,----r--r----,--,--- ----

GNI GO T1 T2

I I

/

I ,

v* P* Tl T2

Y Pt2 P t l - S .

P+2-P

y P+ 1 j J - S

Ptl P+2 1 0 -T

Vtl P+I

I

^{j J - S}

T3

no

I \ Til n2

, \ \

13 TlO

8 - S 8 - S P t l - S , P t 2 - P INDEX B.

B - S INDEX MB

TI3 T14 TIS

, ,

T LAST GNI GO

5 T. _MD

^T. _MD

_T!

_lAD T1

MD

PDP-8 TIMING

r

DATA DIRECTION IN PDP-8

PROCESSOR

lINC PROCESSOR

CONDITIONS .i. jJ

0 0

0 J60

, °

I

"0

OUT

MB REGISTER

~

SENSE AMPLIFIERS

--- - -

S REGISTER

P P+l P REGISTER

8 REGISTER

----1

A REGISTER

C

REGISTER ~

MEM-B FLIP-FLOPS

J I

- - - - -

,..

/

~Ptll

I I ^{' - '} I I _I I ^I I I I I

\

,

I \

I ,

1 ^Beu ~\@

NDX

J I

I I

- - - - - - --- - - - - -

V* p*

~

^j

I I

*

I ,+..P P*+1

, \ : J

\

Y

NDX \

.It\ r

u. r

'+"

COMP B

a , Oor

BCLA

lINC TIMING

--r--r----.-...e<,-,---"....:3::L....,.----... - . . - - - - ----

GNI GO Tl T2 T3

no

^Til ^{T LAST}

I I I \ ₁ _I

/ \

^GNI ^GO

I , , \

y* P* Tl T2 13 TIO

V P+2 P+l-S.

B - S P+2-P

Y P+ 1 j J - S 8 - S

P+l P+2 10--T P t l - S .

P+2-P

Y+l P+l fJ-S INDEX 8,

B - S INDEX MB

(9)

PDP-8

1

PROCESSOR

L1NC PROCESSOR

Tl MD T1 MD

MD

TI

MD

PDP-8 TIMING --''--_'--_ _ _ . 1 . . - _ ....

- - -... ---'---'----'----

IN DATA DIRECTION

OUT - - - -

MB REGISTER

SENSE AMPLIFIERS

S REGISTER

P REGISTER

8 REGISTER

A REGISTER

C REGISTER

MEM-B FLIP-FLOPS

----1 _•

- - - - - -

P P+I

---1 ,

----1 -1

1 I

- - -

- -

,..

I }P+1l f

f ^~

I I _I I ^I 1 I I

\

\ 8eOl

f3 b

""'

NDX

I 1

I

•

^I

- - -

-

y* p*

~ •

f I *

I ..+-P P*+1

,~

\ Y NDX \

~ , r 1

'+' I

0

, o

¥r

8COA

¥ ; OR (EXCLUSIVE)

I I

----

LI NC TIMING

-.---.---r-...::.< ... , ---'"""'T,,,...;:::..---.---.---.,...---

GNI GO

/

Tl I

T2 I

T3 TIO

I \ Til TLAST

I I

\

^GNI ^GO

CONDITIONS

" ⁺ ⁺ ^\

i

fi y*

p* Tl T2 T3 TIO

0 0 ^y P+2 P+l-S,

8 - S I P+2-P

I

0 .. 0 y P+l

fi-S

B-S

1 0 P+l P+2 1 0 - T P+I-S,

Pt2-P

I

.. 0

Y+I P+l

fi-S

INDEX MB ^{INDEX B,} B-S

6

Tl MD TI MD TI MD TI

MD

PDP-8 TIMING ~IL-_L-____ LI __ - L _ _ _ _ _ _ ~ _ _ ~I ______ ~ __ ~ ______ _

1

DATA DIRECTION IN PDP-8

PROCESSOR

LINC PROCESSOR

CONDITIONS

I

ⁱ

^I

^fi

0

I

0

0 '""0

I 0

I """0

OUT - - - -

MB REGISTER

SENSE AMPLIFIERS

S REGISTER

P REGISTER

8 REGISTER

A REGISTER

C REGISTER

MEM-B FLIP-FLOPS

----1

^J NDX

~ ^I

I

t

_I

- - 1 - ^{- -} ^-

^{- - -}

_y* ^{- -}

^{- - -}

^{- - - -} _p*

^-

~ ~

^J

I I I I *

P*+I P P+I

I ^~P+l) I t±-,P

I ^'C/ , ^~

I \

\

I _I ^YNDX

*'

^r ^{a Vr}

----1

_I I '¥

I

•

\ a aVr

I BCOA

\

\ V ; OR (INCLUSIVE 1

\

----1

^BCLi

^/3 ^b

^'C/ ^I^I

LI NC TIM I NG --;r---r-j _____

-._"-c

T"j ---.I'!...;:s".-.---r----r---- GNI

I

i

I

y*

I

^P*

I!

I:

^y

^!

^I ^P+2

i i y

I

^{P+ I}

I I

i

^P+2

II

^P+I

!

I

I' ^Y+I

!

^P+I

GO T1 T2

I I

/

" ⁺

II

^T1 ^T2

I [ I

¹_'P+2-PI^P+l-S,!

II

ÎÎ^{f i - S} ⁱÎ

li

^lO^- ^T^I^I

ⁱ

T3 I

+

13 TIO

\

!

I I

\

Tl0 8 - S 8 - S

Til T LAST I I GNI GO

.

!

: I Ptl-S,!

I

Pt2-P I

II

_II fi - S INDEX B,I I INDEX MB I B-S

(10)

TI MO Tl MD Tl MD TI MO TI 1.10 TI MD TI MO PDP-8 TIMING __ ~~~ ____ ~ __ ~I ______ ~ __ ~ ______ - L __ -L ______ ~ __ ~ ______ ~ __ ~ ______ ~ __ ~ ____ __

DATA DIRECTION IN

i - - - - - ~

PDP-8 PROCESSOR

lINC PROCESSOR

CONDITIONS

.i. jJ

0 0

0 liO

I 0

1 liO

OUT ____________________________________________________________ -L' - - - - - ~,---

NDX

~

P REGISTER

I I P Ptl _I )Ptll

I ^~

I

1 I I

,

^Y^NDX

- - I

I I 9 REGISTER

I I A REGISTER

I I

\

I

~

I I

*

I ,+,P

,,,,,

\

»- ..

oi

r

' f ' If

Y

.--.--i

I I I I

@ I

- - - - j - - -

I

n* ...

I

j~

I

^P*+1

I I .l+4

=

+4

CLR A7-11

Z REGISTER

---~lf---\-\ ---1

'SCi;'-",

C REGISTER

--1 -

~

t

SHIFT

MEM-9

-i

FLIP-FLOPS

----

LI NC TIM I NG

-r---,r---__,--""'<~i---ri'!...::s..-r---"""T'"--

...

cfF---,----,---~----r---=-r?'~--r---

GNI GO

'1'* p*

'I' P+2

'I' P+ I

P+I P+2

'1'+1 P+!

/

I

TI

4 - T Tl

/ T2

I

•

T2 P+I-S, P+2-P

j J - S

T3 T4 T5

no

Til T12 TI3 T14 T15 T LAST

I \ I I I

I I GO

N-O

I Blz 0 - 9 I

\

^N

^t

0 l O - T

<D

N -I+N 17 lO-T

N -I-N

-

+ ^\

';6

^lO-T

12

®

13 T4

B-S

11 10-T

B-S

@

P+I-S,

' 9

^10_T

• ^:3

² 10-T,N-!.N

^®

I

^{SET WR} ¹ ^GNI

P+2-P INDEX B,

INDEX MB B-S

7 <D

^{O-A 7-11}B t 4-+8 ^II

I®

^{IF ZII}^~I, THEN ON ^---j^I I INTENSITY, 0 - Zl1

i

IF ZI'

=

0, THEN OFF I INTENSITY, A+4+A, N-I-N AND ZSHR

®

IF ZII = " THEN ON INTENSITY, O-Zl1 !

IF Z11 ~ 0, THEN

i

0+A7-1', B+4-B, I

N-l-N, OFF

i

INTENSITY, AND ZSHR

!

(11)

PDP-8

1

PROCESSOR

LING PROCESSOR

I

T1 MD PDP-8 TIMING

IN DATA DIRECTION

OUT

MB REGISTER

---I

SENSE AMPLIFIERS

- - - ^{- - -}

P S REGISTER

P P+' P REGISTER

B REGISTER

--I ,

A REGISTER

C REGISTER

---I

MEM-B ---1 FLIP-FLOPS'

T1 MD T1 MD T1 MD T1 MD TI MD T1 MO Tl MD T1 MD

NDX

I ^I ~ I I I I I I

J I

^I ^I

•

Î Î Î Î ^~~ Î

- - - -

^{, - - -}

- - ^{- - - -} - - - - - - - - - - - - - - - - -

a P +1

I~

P+2

,Ir ^NDX

I I h, X (+ 1) _I

I I I

Y

~ DISia IO-N

I

--- --

LING TIMING

~Ir--'---~---.---r---r---or--'---'-~~T--~---r---r---,r--'r---.---.---~--_,

GNI GO T1 T2

n

T4 T5 T6 T7 Tl0 TIl T12 T13 T14 T15 T'6 T17 T LAST

I

!

^GIO

*

N

0 N-l-N 'O-T h=O ON INT 0 h = 1 ON INT 1

- --

^-

8

(12)

PDP-a

r

PROCESSOR

I

I LINC PROCESSOR

Tl '-lD T1 '-lD T1 '-lD

PDP -8 TIM ING _"--_'--_ _ _ .L..._"--_ _ _ - ' - _ - ' -_ _ _ IN

DATA DIRECTION

OUT - - - '

""P ~

SENSE AMPLIFIERS MB REGISTER

----~l+.~---++--- ---1

- -

- - -

S REGISTER

P P REGISTER

B REGISTER

---1

C REGISTER

----1

MEM-B

-I

FLIP-FLOPS

Pt1

- - -

1 ""PX - -

I I

= J'C~

•

^k:;.'C' ^J

- -

r- - -

- - -

X

~

X X+1

JMP

P+f J

I

LI NC TIM ING

_1..---..---..---.---.,....--.,....----

GNI GO

x

X #

°

Tl I

,

I

n

X ' 0 I GNI I O - - P

I T2

\

,

I T2 P - B B _ P T LAST

GO

T3 T LAST I GNI GO

9

Tl MD TI MD TI MD TI MD TI MD Tf MD

PDP-8 TIM ING I

1

^DATA⁰¹^RECTION IN PDP-8

PROCESSOR

LlNC PROCESSOR

COND TIONS

o o

o

#0

o

.. 0

OUT ---~

MB REGISTER

---1

^NDX^{(. )}

S REGISTER

- - - r - - t - - - : : ; . - - - + - - - , : r - - - 4 - - - + - - . - - - -

P Ptl I(PttJ

B REGISTER

---1 t

^Y^NDX

'----+( ... )!---<~ atr+1

at r+ I

A REGISTER ---+---'--+----~---

BCOA CARRY

,

I

LINK - - - -

-1- \ ---

L",~\@

- -~I~l---

C REGISTER

---1

MEM-B FLIP-FLOPS

----

LINC TIMING

~Ir_-rl ----r~<~I---~I~~~----~--,----.r---.----r--r---

y*

P+1 y+\

GNI GO Tl T2 T3 TID

P+2 Pt 1 Pt2 Ptl

/ I I \

/

T1

I

^T2

I i

^ft-S

1,0-T:

T3

INDEX B, INDEX MB

Til

\

TIO

B--'S Pti--'::'S, Pt2--+P

Tt2

"

TI3 T\4 TI5 T LAST

I I

GNI GO

(13)

PDP-8 PROCESSOR

LlNC PROCESSOR

j

TI MD TI MD TI MD TI MO

PDP-8 TIMING ---''---''---'-... - - - ' - - - - ' - - - -... - - ' - - - - IN

DATA DIRECTION

OUT - - - - Y NDX

----1

ÎÎ ÎÎ ÎÎ

M8 REGISTER

SENSE AMPLIFIERS

- - - -

-

- - - - - - - -

V* p*

S REGISTER

~ ~ •

I I f I

*

_P*+I

P P+I f ~p+1) I

.-r.

^P

I ^~ ^.~

\ P REGISTER

I \

- - I

I Î ÎÎ

^r

^{V NDX}

^»..

'+' ^{, r} ^~I 8 REGISTER

I

I a ~ r

I ^I BCOA

A REGISTER

I

\ I

\

----1

LDA" {3

b

I

""

^I

C REGISTER

MEM-8 ~

FLIP-FLOPS

LlNC TIMING I

I

^<

I

'!.

GNI GO TI T2 T3 TIO TIl T LAST

I I I \ I

/ \

^GNI^I ^GO

CONDITIONS

i , ₊ \

.i.

J3

^V* ^P*

I

^TI ^T2 ^T3 ^TID

0 0 ^Y ^P+2

I

^P+I-S,^P+2-P ^{8 - S}

0 '*0 ^Y ^P+l ⁱ

J3-S

^{8 - 5}

1

°

^P+I ^P+2 ^{l O - T} ^P+l-S,^P+2-P

1 '*0 ^Y+I ^P+I

p - S

INDEX MB ^{INDEX 8,} 8 - 5

10

TI MD TI MD TI MD TI MO

PDP-8 TI MING - ' - - - ' ' - - - ' -... - - - ' - - - - ' -_ _ _ ....L_....L.. _ _ _ IN

DATA DIRECTION PDP-8

PROCESSOR

LlNC PROCESSOR

CONDITIONS i

I J3

I

0 0

0 '*0

1 0

I '*0

OUT - - - - hNDX

1018 REGISTER

----1 _•

ÎÎ ÎÎ

~ I

SENSE AMPLIFIERS

I

II

i I

_I

I

- - - -

S REGISTER

P P REGISTER

8 REGISTER

- - I

A REGISTER

C REGISTER

----1

MEM-8 ~

FLIP-FLOPS I

P+I

- - -

,.

I

~P+1l

/

I ^~

I I _I I ^I I I I I

\

\ LDH.i.{3

b

~

- - - --- - -

V* p*

~

I I

*

I

.-r.

^P ^P*+I

, ' - 0 /

\ Y hNDX \

».. ,

_I

'+' 1

~

I

'-.J

I I

I

'!.

LlNC TIMING _r----,r----.,-""'<~I---r..:::!L..,..---....,....-....,....---

GNI GO TI T2 T3 TIO TIl T LAST

I I I ^\ _I _I

/ \

^GNI ^GO

I , ₊ \

Ttl T LAST

V* P* TI

I

_I _T2 _T3 _TlO

0 8COAL AR-AL

Y

i

P+2 P+I-S, P+2-P

!

B-S I BCOAR

Y P+ 1

J3-S

B-S

P+l P+2 10_T P+I-S,

P+2-P

Y+I P+I

J3-S

h INDEX B

h INDEX M8 B-S

(14)

PDP-8

I

PROCESSOR

LINe PROCESSOR

I

T1

MD T1 MD TI MD T1 MD

T1 1.40

PDP-S TIMING ~~~~----~--~---~--~---~--~---~--~---

IN DATA DIRECTION

OUT ---~

M. REGISTER

~ I

^JMP

r

SENSE AMPLIFIERS _

-1--1--1- -

^p

^t=-

S REGISTER

P P+l P REGISTER

B REGISTER

~

SET LMB SYNC

FLIP - FLOP

- - -

U.48 REGISTER

LMB SETUP REGISTER

e REGISTER

~

MEM-B ---1 FLIP-FLOPS •

,

- - - - I

I

, LMB N

P+l I P+2

I

P+2

=

^PH

~

)

I

•

^~ ^I

I ^'>J I

I

~ N

J , JMPX (X -FO) J

I I

LI Ne TIM ING

--.j----r---.---.---.----.---"'T"""--"'T"""---"T"""--T"""---

GNI GO Tl T2 T3 T LAST

I I

GNI GO

THE JMP INSTRUCTION IS SHOWN BECAUSE COMPLETION

TI /

/

T2

\

T3 T LAST

I I

GNI GO

OF AN LMB INSTRUCTION COMES DURING THE JMP INSTRUCTION.

A JMP MUST OCCUR SOMETIME AFTER. BUT NEED NOT BE THE NEXT INSTRUCTION FOLLOWING AN LMB INSTRUCTION.

1 1

PDP-8

I

PROCESSOR

LlNC PROCESSOR

T1

MD T1 MD T1 MD

PDP-8 TIMING _~_~ _ _ --I_~ _ _ _ _ _ __L _ _ __I.. _ _ _ _ _ _ _

IN DATA DIRECTION

OUT - - - -

MB REGISTER

--1

r - - - - i

SENS~MPLIFIERS

^_

-1--1-__ _

S REGISTER

P P+l P REGISTER

B REGISTER

~

A REGISTER

-- - - --

Z

REGISTER

- - - - -

R REGISTER

---

LINK

-- - ---

C REGISTER

~

MEM-B ---1 FLIP-FLOPS'

P + 1

P+2

,

_~

I

---411 ,

I

I \

---+11

t @ I

\ I

\ ^/

---+p _~

---+11

MSC N

I I

LI Ne TIM ING

--.jr----,---.,.----.---.----.---

GNI GO T1 T2 T3 T LAST

I I GNI GO

N MNEM T2 T3

0 HLT til-RUN INT til-AUTO FF

5 ZTA Z - A ASHRPLS

11 CLR O-A,O-L

0 - - Z

14 ATR O-R A - R

15 RTA O _ A R _ A

16 NOP

17 COM A _ _ A

(15)

T1

MD Tl MD T1 MD

T1

MD Tl MD TI MD PDP-B TIMING ~~~~ ____ ~ __ ~ ______ ~ __ ~ ______ - L _ _ -L ______ -L __ ~ ______ ~ __ ~ ____ __

IN DATA DIRECTION PDP-8

PROCESSOR

LlNC PROCESSOR

1

CONDITIONS

.i fJ

0 0

0 ~O

1 0

I

!

^tlO

I

OUT - - - - NDX

MB REGISTER

--I

ÎÎ ÎÎ Î j~ I ~ ÎÎ

SENSE AMPLIFIERS

!

^I

- - - - - - - - - - --- - - --- - ^--- - - - -

Y*

S REGISTER

,. ~

P P+l _II

~P+l)

I ^{I I},.t.,P ^*

I ^'V' , " J

\ P REGISTER

I \

I _I ^{Y NDX}

»..

^r

---1

_I ^I '+'

B REGISTER

I

I a.

A REGISTER

I

\

\ -'

\

,

Z REGISTER

\

\ _AO-L

LINK

--- ---,---

C REGISTER

--I

MEM-B ~

FLIP-FLOPS

Y* P*

Y P+2

Y P+ 1

P+l P+2

Y+l

!

P+I

!

^I

\ ' MULiP

b

'V'

<

I

I T1 T2

I I

/ \

I + , \

Tl T2 T3 T4

! ~!~-=:~,

^B-S

fJ-S B-S

4 - T P+I-S,

P+2-P f J - S INDEX B.

B-S

I IN[)E)( uS

12

p*

P*+1

,,,, r

I 101

..-=-. r-"o I

'I'

tt

^{' ¥}

^'f'

^I

iBCOA ICARRY 10.1

t

^' ^(pSHIFT

I

"lrI ~

^SHIFT

"'"

^I

Z-A

~

10-N

.1

I I

T6 T7 T11 TI2

I

\

N

.. ,

"

0 IFZII=(l1 IF Zil = (I) SHIFT A REGISTER

"-

"- 17 THEN THEN SHIFT Z REGISTER

1 16 BCOA CARRY

1

+ +

N - l - N

1 6 l O - T

I

IF h = 0 IF h = 0 N - l - N

1 5

THEN Z-.A ASHRPLS l O - T 1 4 IF LINK =(1)

GNI

T LAST, GO

~

^{COMP A}

!

IF BO = (1)

I

COMP B, COMP L1NC

I

IIF AO = (1)

I

^{COMP A}

1

(16)

PDP-B

r

PROCESSOR

L1NC PROCESSOR

TI MD Tl MD

T1

MD

PDP-B TIMING IN DATA DIRECTION

OUT

MB REGISTER

---1

_~ ^J^I

• I

SENSE AMPLIFIERS

- - - --- - - - -

B REGISTER

---t

A REGISTER

Z REGISTER

LINK

C REGISTER

---t

MEM-B --' FLIP-FLOPS '

P+l

~,

•

^ROL.iN

P+l

~

P+2

,

_I

I

+-- +--

I

,

- ^,

I

-

, I -.1

I I

10

JI---w',

L1NC TIM ING --'I~--'r----~I:""-"'''Tr,---...:..:;.

... , ... - - -

GNI GO T1

N ~--

*0 ROT LEFT PULSE N-I-N 0

TIl

•

I ^{T LAST}^GO^I

ROT LEFT PULSE N -1-N,IO-T

GNI

LINK IN SHIFT PATH IF.i.

=

1

13

PDP-B

r

PROCESSOR

LlNC PROCESSOR

TI MD Tl MD Tl MD

PDP-B TIMING IN DATA DIRECTION

OUT

MB REGISTER

---1

ÎÎ ÎI

SENSE AMPLIFIERS

- - - - - - - - ^-

S REGISTER P+t

•

P P+l P+2

P REGISTER

B REGISTER

---t

A REGISTER

Z REGISTER

LINK

C REGISTER

---t

MEM-B --' FLIP-FLOPS ---.

•

1 ROR.i.N

-

I

-

I I

-

^II I

1-1 I

,

_I

-

I, I

-

₁I

-

I I , -1

I

I I

10 . . - - - , " ' ... ,

LI NC TIMING --,~--,r---.:.;I:....--.crT'~--:.::~,-:.-.

... - - - -

GNI GO Tt T10 Tl1 T LAST

N

: ""GO

. ^"

^~

ROT R PULSE ROT R PULSE

#0 ASHR PULSE ASHR PULSE N - I - N 1 0 - T

0 GNI

LINK IN SHIFT PATH IF J.; 1

(17)

PDP-8

1

PROCESSOR

LlNC PROCESSOR

TI MD TI MD T1 MD T1 MD T1 MD

PDP-8 TIMING ~~~~ _ _ ~_~ _ _ _ ~_~ _ _ _ _ - L _ _ - L _ _ _ ~_~ _ _ _ _ IN

DATA DIRECTION

OUT - - - -

MB REGISTER

----1

SENSE AMPLIFIERS

- - - -

S REGISTER

~ P P REGISTER

B REGISTER

----I

A REGISTER

C REGISTER

----1

MEM-B

--i

FLIP-FLOPS

P+l

I NDX r J ^r J

I I I _~ I

- - - - - - - - - -

Y*

~ ~

^~

I

~P+l)

/

f I *

I /hP +1 +1

I ^-.:;J , , " ,

I \ \

I _I ^{Y NDX} )to.. , r ~ r I

I ^I ^'+"

I

a

_r-¥o (]

I BCOA BCOA

,

\

\ ^:y.⁼OR (EXCLUSIVE)

\

\ SAE.i

13 h

T1 /

'"'

<

I T2

I

----

^T3^I

"

I

J I

TID Til T12 Tl3 T LAST

\ I I

\

^GNI

_I

^GO

-

CONDITIONS

/

i ₊ ₊ ^\

.i. jJ v* P* TI T2 13

no

0 0 y P+2 P+I-S, B-S

I P+2-P

0

,to

Y P+l j J - S B-S

I 0 P+I P+2 10-T P+I-S,

P+2-P

I

"0

^Y+I ^P+I ^{j J - S} INDEX MB ^{INDEX B,} ^B-S

PDP-8

1

PROCESSOR

LlNC PROCESSOR

I

14

T1 MD PDP-8 TIMING

IN DATA DIRECTION

OUT

MB REGISTER

----I

i

SENSE AMPLIFIERS

- - - -

S REGISTER

P P REGISTER

B REGISTER

----1

A REGISTER

C REGISTER

----1

HOLD SAMPLE

MEM-B

--i

FLIP-FLOPS

P+I

,

T1 MD

I

I _~

- - - -

I

1

I

SAMla.

TI MD T1 MD T1 MD T1 MD

J J

J I

I I I _~ I

r - - -

- - -

P+I 4

P+2 ROT B

-

I _I III

I - B 0 3

f

J ^I ^CVTPLS

•

O_N I

I

,- ^{- - ,}

LI NC TIM ING --,~--,---_r--_r---_r--"'"T'"---"'T""--"'T""---T"""--'F_---'t____,r__----

l

GNI GO

TI T2 13 T4 T5 T6 T7 TIO Til T LAST

I I I

+ ^!

^GO

1,~ I

^{[ 10-+T}

1

16 I N-l __ N,

15 CONVERT

i 1~ PULSE

10 GNI, CONVERT

PULSE

I

(18)

PDP-8 PROCESSOR

L1NC PROCESSOR

I

^SET.L

^a I

T1

MD Tl MD Tl MD Tl MD Tl MD

PDP-8 TIMING ---"'--...1 _ _ _ -'-_....&... _ _ _ ...1.-_"--_ _ ...1_---'-_ _ _ - ' - _ ... _ _ _ IN

DATA DIRECTION

OUT ---~

t

SENSE AMPLIFIERS MB REGISTER

-~~---@f~--@)-f

~

^---t-+---

- - -

S REGISTER

j

P P REGISTER

B REGISTER

- - l

C REGISTER

~

MEM-B

-.J

FLIP-FLOPS'

P+l

I

- - - -

P +1

•

Pt2

I I

SET.L a

,.-

<

j T1 T2

I I

r - - - - -r - - -

- -

r - - - - -

y*

a P+2

f1~

\

^\

" " , I Pt3

'-"I

I

Y

d

_{' III} ^I

'-" I

I

-..

;!,

j j

13

no

^T11 T12 T13 T LAST

I

I I

GNI GO

15

PDP-8 PROCESSOR

L1NC PROCESSOR

T1

MD T1 MD TI MD

PDP-8 TIMING _L..-...IL...-_ _ ....L_ ... _ _ _ -'-_.L.... _ _ _ IN

DATA DIRECTION

OUT - - - -

MB REGISTER ~

SENSE AMPLIFIERS

---~+~---~++--- - - - - r - - - - - ^'"

S REGISTER P+l

~

P P+l P+2

P REGISTER

- - l , ,.

_I

B REGISTER I

-

I

-

I

I I

A REGISTER

- ^-

Z REGISTER I

III (11

LR.N

LINK

III - ^\11

C REGISTER ~

MEM-B

-i

FLIP-FLOPS

/--..

L1NC TIMING 10

~ ;0,

I I

^j

GNI GO Tl Tl0 Til T LAST

/ /

III

^I

ASHR PULSE

II I

ASHR PULSE

•

^GO

"to

I N - l - N

I

N - l - N 1 0 - T

LINK IN SHIFT PATH IF .i

=

1

0

I

^GN!

(19)

T1 MD T1 MD T1 MD T1 MD T1 MD PDP-B TIMING _L----JL-_ _ ...J_---' _ _ _ - - I . _ - - I . _ _ _ -'-_....L. _ _ _ ... _ ... _ _ _

1

DATA DIRECTION IN PDP-B

PROCESSOR

L1NC PROCESSOR

CONDITIONS i

I

^jJ

0 0

0 _0

I 0

,

_0

O U T - - - - hNDX

MB REGISTER

- - I

^J¹ ^~¹ ^~Î ÎÎ

SENSE AMPLIFIERS

0 I

-- - -

S REGISTER

•

P P REGISTER

B REGISTER

----i

A REGISTER

C REGISTER

- - I

MEM-B

-I

FLIP-FLOPS

P+l

- - -

~

I

~P+1l

I I

...,

I I _-.J I ¹ I I I

\

\ rSHD.iB

b

~

- - - - - - - - - - - -

y*

.'"

^j

I I

*

I J±.,P +1 +1

...

I

,

Y hNDX

~ r

_I

...

I

~

lIr

~

\.!J

BCOA BCOA~

I I

----

L1NC TIMING

_r----,r---.,-..:<'j---"""T, ... ..;:::s.--r----r-"T"---.--.---

y~

'I' 'I' P+l '1'+1

112 AR=AL

GNI GO T1

I T2

I

,I •

P* T1 T2

P+2 P+l-S,

P+2-P

P+l j J - S

P+2 lO-T

P+l j J - S

T13 T LAST AL ,;. 0 I AR-AL P + l - P -

AR",O

1

P+l-P

13

I

+

13

h INDEX B h INDEX MB

Til

\

T10 B-S B-S P+l-S, P+2-P B-S

T12 Tl3

I GNI

T LAST I GO

16

PDP-a PROCESSOR

LlNC PROCESSOR

I

1 I

SKP .. N

I

T1 MD Tl MD Tl MD

PDP-a TIMING _'--_'--_ _ ---1_---' _ _ _ ---'_---1. _ _ _ _ IN

DATA DIRECTION

OUT - - - -

MB REGISTER

- - f

_~ ^I^I j

SENSE AMPLIFIERS

- -

- - - -

f - - S REGISTER

~ P P REGISTER

B REGISTER

- - I

C REGISTER

- - f

MEM-B

-l

FLIP-FLOPS

P+l

' I

l-

~

^"PiN

I I

- - -

.~

+1

I 1

L I NC TIMING

--.--.,r---...,-...,---"""T---y----

GNI GO TI T2 T,3 T LAST

I

GNI

GO

i

+

0 P +1-P IF CONDITION IS TRUE ¹_I 1 P +1-+P IF CONDITION 15 NOT TRUE!

N CONDITION MNEM 0 I 5S 0 = (1)

J

1 5S1=(I) ^I 2 5S2=(1)

I

3 SS 3

=

^(I) 4 SS 4

=

(I) I

5 555=(1) 6

1 I

⁷^I

i 10' IAI

=

0 AZE

~ I I AO = (0) APO 12 LINK {OJ LZE _I

1'3 !'BMARK IIBZ

114 I FLO (1) I FLO liS I Z11

=

⁽⁰⁾

I

ZZZ

i 16 •

I

(20)

PDP-8 PROCESSOR

-+-

L1NC PROCESSOR

T! MD Tl MD I i MD T1 MU Ti iftD

PDP-a TIMING ~I __ ~I ______ ~ __ ~ ______ - L __ - L ______ - L _ _ ~ _ _ _ _ _ _ ~ _ _ ~ _ _ _ _ _ _

IN DATA DIRECTION

OUT ---~

MB REGISTER

---1

SENSE AMPLIFIERS

- - - -

B REGISTER

- - l

C REGISTER

---1

MEM-B

-l

FLIP-FLOPS

P+I

-

I I

- -

~

I

~P+l)

,

I ^{' - '} I I _I I ^I I I

\

NDX

I I

.r-i

I

J

^I

- - -

- - - -

Y*

~ •

I I *

I /hP +1 +1

, ' - '

\

\ ROT B

Y NDX

)t., ^{' ¥}

.t -

-

L1NC TI MING - - - , r - - - , - - - y - . t : . < T I - - - _ . _ I " . . : : L . - . - - - . - - . - - - . - - - . - - - - -

----

GNI GO

/

T1 I T2

I

\

Til Tl2

\

'\

\

Tl3 T LAST I I GNI GO

CONDITIONS

I + , \

.i. jJ v* P* Tl T2 13 TIO

0 0 ^V P+2 P+l-S, B-S

P+2-P

° ^"0

^Y ^{P+ 1} ^jJ-S ^8-S

I 0 P+I P+2 1 , 0 - T P+I-S,

P+2-P

I

"0

^Y+l ^P+l

I

^jJ-S ^{INDEX MB}^{INDEX B,} ^8-S

17

I i MD I i MD I i MD Ti iwlD I i MD

PDP-8 TIMING ~~~ ______ ~ __ ~ ______ - L __ - L ______ - L __ -L ______ ^~__ ^~____ __

IN DATA DIRECTION PDP-a

PROCESSOR

-+-

L1NC PROCESSOR

CONDITIONS

.i.. jJ

a a

0

"0

1 0

1 .. 0

OUT ---~

MB REGISTER

---1

SENSE AMPLIFIERS

- - - -

S REGISTER

•

P P REGISTER

B REGISTER

- - l

A REGISTER

C REGISTER

---1

MEM-B --.J FLIP-FLOPS I

P+l

J

I

- - -

I

~

I

~P+1l

I I ^{' - '}

,

I I _I I ^I I I

I

I \

t

^STA.i{3

~

NDX

I I

I

•

^I

- - - - -

Y*

~

I I * I /hP , , - ,

\

Y

NDX \

,It,

a

' ¥

a

r--1

- - - - -

p*

•

P*+1

I I

LINC TI MING

-1r----"r---,-..t.<~I---"TI"~-.---.-- ----

^....- - - - . - . . , . - - - - -

GNI GO Tl T2 T3 TIO Til TI2 T13 T LAST

I I I \ I I

/ \

^GNI ^GO

I + , \

v* p* Tl T2 13 TIO

Y P+2 P+I-S. P+2-P B-S

y P+ 1 j J - S B-S

P+l P+2 1 0 - T P+I-S,

P+2-P Y+I P+I

p-s

INDEX MB ^{INDEX B,} B-S

(21)

PDP-8 PROCESSOR

LlNC PROCESSOR

I

TI MD T1 MD TI MD

PDP-8 TIMING _.1...-_.1...-_ _ - - ' ' - - - - ' _ _ _ --'_--1. _ _ _ _ IN

DATA DIRECTION

OUT - - - '

MB REGISTER

----l

SENSE AMPLIFIERS ----~~---+---

P

x

P+I

S REGISTER

---.,...---.,f---"""7----t---r---

P+2 P REGISTER

- - - i o I I t - - i - - - f - - - + - - @ ; f - - -

B REGISTER

----1

A REGISTER ---i--_+_~

C REGISTER

----1

MEM-B

-I

FLIP-FLOPS

L1NC TIMING

_r---.,r----"""'Tj-"""'T---"""'T"--r---

GNI GO T1 T2 T3 T LAST

I I GNI GO

PDP-B

r

PROCESSOR

LlNC PROCESSOR

I

Tt MD PDP-8 TIMING

IN DATA DIRECTION

OUT

MB REGISTER

----1

SENSE AMPLIFIERS

- - - -

S REGISTER I P P REGISTER

B REGISTER

----l

A REGISTER

C REGISTER

----1

MEM-B

-I

FLIP-FLOPS

P+I

,~

Tt MD

J

I

- - -

~

I

~P+t)

I I ^'-"

I I _J ^~ I ^I I I

,

\

\ STH..i,8

h

'-"

TI MD

hNDX .J

1 ~

- - -

y*

~

I I

*

I ,-t..,P ."'-'

\ Y hNDX \ ~

W

HALF

III

I

T' MD T1 MD TI MD Tt MD Tt MD

,

¹

r l

- - - - p*

,~

P*+I

1 1

1'.'\ fI\

,I

\!.JI

1 I

---

LlNC TIMING

-r----.,r---,-..:<'j----.j3..:3..-.---.,--.,----... - ... - - -. . -T""---r--,----,r--,-

GNI GO TI T2

I I Tt3 T LAST

I I T3 TlO

I \

Ttl TI2

/ \

^GNI ^GO

i

CONDITIONS

I • ⁺ ^\

^TIO ^TIt ^T12 ^TI3

i

P

^y* ^P* ^Tt ^T2 ^T3

a a

^y P+2 P+I-S,

B - S P+2-P

0 '*0 ^y P+ I

p-S

B - S

f 0 P+f P+2 l O - T P+I-S,

P+2-P

I

¹

I

'*0

! I

^Y+l P+l

!!

^{. 8 - 5} ^!,II 11'1 UI:,.A MO,

~ !~P .!

^{8 - 5}

!

18

(22)

PDP-8 PROCESSOR

L1NC PROCESSOR

\SXU N I

T1 MD TI MD Tl MD

PDP-8 TIMING _"----I"-_ _ ....L._-'-_ _ _ ...I.-_.&... _ _ _

IN DATA DIRECTION

O U T - - - -

MB REGISTER

---1

SENSE AMPLIFIERS

----~+~----~+tr--- _{- - -}

B REGISTER

--1

C REGISTER

--1

MEM-B

--..J

FLIP-FLOPS

I

P

P+I

- - - - r - - - -

I'

,1\ +1

' I

r

_I

I

SXL.iN

J I

LINC TIMING

--"r---,.---'"T"-"T""---r--r----

GNI

GO

TI T2 T3 T LAST

I I

GNI GO

CONDITION MET AND.i

=

0 N 0 1 2 3 4 5 6 7 10 11 12 13 14 15 -16 17

CONDITION XLO XL 1 XL2 XL3 XL4 XL5 XL6 XL7 XL10 XU1 XL12 XL13 KST (1)

MNEN

KST

19

PDP-8 PROCESSOR

L1NC PROCESSOR

T1 MD T1 MD T1 MD

PDP-8 TI MING _L..----' _ _ _ - ' - _ - ' -_ _ _ ""'--_01--_ _ _ IN

DATA DIRECTION

O U T - - - -

MB REGISTER

---1

SENSE AMPLIFIERS - - - -....

+lti---toI+.,...---

- - -

S REGISTER P

P P REGISTER

B REGISTER

--1

UMB REGISTER

C REGISTER

--1

MEM-B

--..J

FLIP-FLOPS I

P+I

- - - -

^~----

P+l

P+2

1

_~

I

LlNC TIMING --,r---,.---"'"T""-~----r--r__--

GNI GO TI T2 T3 T LAST

I I

GNI GO

(23)

PDP-8

1

PROCESSOR

L1NC PROCESSOR

I

T1 MD Tt MD T1 MD Tl MD

PDP-B TIMING _ 1 -__ 1 -____ ---1 __ ---1 ______ --1. __ ---1. ______

--1._-'-_ _ _

IN

DATA DIRECTION

OUT - - - -

I NDX

I ~.

MB REGISTER

----1

^I ^j~ ¹ ^j ^I

SENSE AMPLIFIERS

- - - - - - -

S REGISTER

P P REGISTER

B REGISTER

----1

C REGISTER

~

P Q

~ P+l

l---i

XSK.i. Q

--- -- -- - - - -- -

~ +1 +1

X NDX X+I _I

I

I I

lINC TIM ING -r----,Ir---,---,---~-_,_---__._-__r---

GNI GO Tt T2 T3 T4

I I

T~ T LAST

I I

GNI GO I

INDEX P IF B02-Bll =1777

20

PDP-B

1

PROCESSOR

LINC PROCESSOR

I

T1 MD PDP-B TIMING

PDP-B ADDRESS

LINC PDP-B BREAK

MB REGISTER

----1

^j

SENSE AMPLIFIERS

- - -

S REGISTER

P P+l P REGISTER

Tt MD

I I

8 EXECUTE CLASS MTP OPR EXC

Tl MD

I

j ^I j

Tl MD

I I

--- r - - - -

----1 ^•• ••

B REGISTER

A REGISTER

L RUN

--i

^I

L BREAK

C REGISTER

----1

I I

II NC TIMING

-r----.---,---,---.,..-...,..----.---r---.--

PDP-8 ANSWERS PROGRAM INTERRUPT REQUEST CAUSED BY MTP, OPR OR EXC INSTRUCTION EXC, OPR OR MTP WILL GIVE "HOLD" LEVEL

WHICH PREVENTS CONTINUATION OF L1NC AFTER GNI. THE PDP-B RUNS PROGOFOP TO INTERPRET THE INSTRUCTION AND THEN RETURNS CONTROL TO THE lINC BY RESTARTING THE lINC.

MAINTENANCE MANUAL