Varactor Module Characterization

For thick film varactors mounted on a PCB holding the DC biasing network (varactor module), a generalized fixture is developed, which is also used to characterize circuit integrated bulk ceramic varactor modules. The fixture consists of a metal ground plate with

(a)Side view of the module characterization fixture with the spring loaded inner conductors slightly standing out of the two ports.

(b)Top view of the whole measurement setup with the impedance analyzer in the back, the protective bias tee, the balun and the fixture in the front.

Figure 3.8: Designed varactor module characterization fixture and setup.

a size of 250 mm×150 mm and a framework with a height of 170 mm attached to it, holding two custom spring loaded contact connection ports based on the 7/16 HF coaxial standard.

The two ports are fed from the single measurement port of the impedance analyzer and hold a signal-ground (SG) configuration on one port and a ground-ground (GG) setup on the other port. The separation of the single port to the two port setup is accomplished with a custom made balun based on coaxial standard type N. To characterize a varactor module, it is mounted on the fixture and pressed against the spring-loaded inner connectors of the two ports of the fixture. Main advantage of the setup is the shielded environment of the signal path up to the connection point to the varactor module. The two ports of the fixture are guided on metal shafts, therefore it is possible to adjust the distance between the ports to characterize PCBs with different sizes. The metal shafts also provide for a low inductance short circuit between the outer ground connectors of both ports, ensuring identical ground potentials on both outer port connectors. Between the ports, mostly free space is available, therefore electric components on the mounted PCB such as DC/RF decoupling resistors or filters do not interfere with the connection scheme. The measurement fixture and whole characterization setup are depicted in figure 3.8

Main drawback of the fixture is the necessity for custom made calibration standards to eliminate parasitics introduced by the connection cables, the balun and the fixture itself, which are only viable for a certain distance between the ports. For every other distance, a new standard or at least a new set of raw calibration parameters has to be obtained. The required calibration standard short, open, load (SOL) is determined by the impedance analyzer. The standards are connected to the inner conductors of the ports, establishing a connection between the ports. Before using the standards for calibration, their raw electrical parameters have to be obtained. Two different methods are presented in this work. One is based on a full-wave simulation of the standards in CST and the other utilizes a partially calibrated 2-port setup to characterize the standards, extracting the raw electrical data from the measurement with a symmetrical 2-port model. Subsequently, the part of the setup

(a)From left: short, load, open. (b) Back-to-back arrangement of the two ports of the measurement fixture with SMA adapters.

Figure 3.9: Module fixture calibration standards and de-embedding characterization setup of the two measurement ports.

Z₁₁−Z₁₂ Z₂₂−Z₂₁

Z₁₂ Z₂₁

(a)2-port impedance matrix equivalent circuit model.

Z11−Z12 Z11−Z12

(b)Reciprocal 2-port impedance model for se-tups with missing ground plane.

Figure 3.10: Calibration standards and back-to-back setup of the two measurement ports of the fixture.

which was excluded from the calibration is measured in back-to-back configuration and utilized for de-embedding the measured data. The designed calibration standards short, open and load, as well as the back-to-back setup of the two characterization fixture ports, are depicted in figure 3.9.

The fixture is extended by a temperature control unit, to guarantee a measurement tem-perature of 50^◦C. This is necessary, as the circuit board integrated bulk ceramic varactors have a Curie temperature of 20^◦C and should be operated in the paraelectric phase at 50^◦C, see section 2.1.1. The implemented control unit is presented in detail in appendix B.2. For the measurement approach, the equivalent circuit for Z-parameters of a reciprocal two-port network serve as the extraction model. The basic two port equivalent circuit model and the derived reciprocal one for calibration substrates is depicted in figure 3.10. The shunt connection ofZ₁₂andZ₂₁to ground is not considered in the final model, as the calibration substrates do not carry a grounded metalization.

After obtaining the two port S-parameter data from the measurement, it is transformed into two port Z-parameters in Keysights ADS. With the model, the one port complex input impedance of the calibration substrate is calculated according to:

Z= ²(Z₁₁−^Z12) +2(Z₂₂−^Z21)

2 (3.2)

The same approach is used to characterize the remaining part of the fixture connectors in back-to-back configuration. The obtained raw data sets of the short, open and load calibration substrates from the CST simulation and the measurement with and without de-embedding of the fixture connectors are depicted in figure 3.11.

Overall, the obtained simulated and de-embedded data sets of the implemented custom calibration standard match. For the open and load standard, the de-embedding of the fixture connectors impacts less, compared to the short standard. Here, the fixture connector accounts for 55 % error in the obtained inductance raw data compared to the simulated inductance. For the ESR, the error determined by the fixture connectors is even larger with 89 %. The reason for this, are the spring loaded connectors, which are not optimized for high frequency conduction. To evaluate the impact of erroneous calibration data on a C, Q, ESR measurement, a±1 % parameter variation of the de-embedded calibration dataL_short,R_short,L_load,R_load,C_open,R_openis performed and applied to a measurement of a circuit board integrated bulk ceramic varactor module. The detailed equations are given in appendix B.1. The results of the evaluation are depicted in figure 3.12.

At 13.56 MHz the resulting error is less than 1.5 % for the capacitance. For ESR and Q-factor a±1 % variation in calibration data leads to erroneous measurement data smaller than 22 % of the real value. The results show a less significant impact of an erroneous calibration data set on capacitance compared to ESR and Q-factor.