Figure 3.14: Large-signal characterization setup with a thick film varactor.
circuitry for high-power operation, such as DC/RF decoupling filtering and DC bias voltage supply, are of main interest. Therefore, a simple, purely transient measurement method is developed and presented, utilizing the RF envelope voltage at a tunable resonance circuit including the DUT capacitance. The measurement is performed with an oscilloscope and the DUT capacitance is extracted from the envelope of the measured RF voltage with a simulation-based RF to capacitance transfer characteristic of the circuit. With this setup, the accurate acquisition of capacitance response times is limited by the oscilloscope bandwidth, the RF frequency, DC bias voltage supply and the DC/RF decoupling filter. The oscilloscope PicoScope 6403D has a 350 MHz bandwidth and a minimum rise time of 1 ns. With a RF frequency of 13.56 MHz, a maximum frequency according to Nyquist criterion of 6.78 MHz can be acquired, corresponding to a rise/fall time of 148 ns. The DC bias circuitry is based on a Keithley 2410 sourcemeter with a maximum output voltage of 1.1 kV. However, due to the output filtering of the source, a minimum settling time of 100 µs for a resistive load is achieved by the source. For large capacitive loads in the nF range, the minimum settling time is at least 1.2 ms. Therefore, a Behlke HTS 151-03- GSM high voltage transistor switch is used as an output stage. The switch features a push-pull stage with a breakdown voltage of 15 kV, a current carrying capacity of 30 A and a rise and fall time of 15 ns. The switch is used to discharge a 10 µF ceramic buffering capacitor to the DUT. The buffering capacitor is charged by the Keithley DC source to 1.1 kV. A waveform generator drives the switch with a 2 s cycling time and 50 % duty cycle. Concludingly, the main limitation factor of the fast transient measurement circuit are the varactor modules themselves, and in particular the RF/DC decoupling lowpass filters, optimized for response times in the 10 µs range, defined by their application in fast tunable high-power matching circuits.
Measurement Principle and Setup
The transient measurement circuit principle is based on a voltage divider between a resistor and a tunable series resonant circuit containing the DUT capacitance. The basic circuit and corresponding voltage behavior over capacitance are depicted in figure 3.15.
The LC resonant circuit is adjusted in a way that its resonance frequency is at the operational frequency of the RF source for an unbiased DUT capacitance. In the presented work, a 13.56 MHz generator is used, which is also capable of handling occurring reflections due to the detunage of the LC circuit from a matching condition. For an exemplary DUT capacitance of 2 nF, an inductance of 69 nH is required to obtain a resonance frequency of 13.56 MHz. It should be noted, that this inductance value represents a lower limit manageable in regard to the size of the inductor. Smaller unbiased capacitance values result in larger, more manageable required inductor sizes. For the transient characterization measurement, the generator voltage as well as the voltage across the LC circuit is measured.
At resonance frequency, the impedance of the LC circuit is exclusively determined by the parasitic ESR of the resonant circuit, while the reactive parts of L and C in the complex impedance cancel out. Assuming resistances in the 100 mΩrange for both L and C, the
RF Source 13.56 MHz, 50Ω
R=50 Ω
DUT
Lres VLC
Vgen
(a)RLC measurement circuit.
1 2 3 4
0 1 2 3 4
Capacitance / nF Voltageenvelopemagnitude/V VLC
(b) Envelope voltage magnitude vs. capacitance in the LC circuit. The resonance frequency of the LC circuit is 13.56 MHz forCDUT=2 nF.
Figure 3.15: Basic circuit for transient measurements and characteristic capacitance re-sponse.
voltage across the LC circuit at resonance is∼0 V. For in- or decreasing capacitance values, the resonance frequency of the LC circuit is detuned, resulting in an increase of the voltage across the LC circuit. From the magnitude of the voltage envelope at the LC circuit, C can be calculated assuming knowledge of all component values and parasitics in the circuit and the input voltage from the RF generator. In figure 3.15, the voltage envelope trace shows a non-unique correspondence between voltage and capacitance. For an automated measurement evaluation, this might create issues in regard to uniqueness of capacitance extraction. Therefore, it is important for the LC measurement circuit to be well tuned to the excitation frequency of the generator. The sensitivity of the LC circuit denoted as:
S= dVLC
dC (3.3)
shows a maximum when the resonance frequency is detuned to higher frequencies. This is the case for decreasing C values compared to the C value at resonance frequency. Therefore, the selection of the resonance frequency in regard to the unbiased capacitance also denotes the operational measurement region of the circuit. In general, both regions left and right from the resonance minimum can be used for the measurement, see figure 3.15. However, the sensitivity of the circuit is significantly increased for DUT capacitances in tuned state below the resonance minimum. The integrated circuit board bulk ceramic varactors are equipped with RF/DC biasing filter solutions for a frequency range up 400 kHz, resulting in a minimum rise time of 10 µs, see section 5.2.1. However, the large ferrite filter coils with values in the µH range and high DC current capabilities introduce significant voltage overshoot when exposed to fast transient, heavy current voltage steps. To prevent these
transients from coupling into the measurement taps, an additional PI filter is implemented in the circuit. The filter consists of two 1.2 µH coils to ground and a 1.8 nF capacitance.
The series capacitance of the filter introduces a DC block in case of a breakdown of one of the DUT varactors. The circuit and the voltage overshoot at measurement tap 2 for a step voltage of 1 kV and a rise time of 1 µs are depicted in figure 3.16.
To provide for a selection of measurable DUT capacitances, the implemented LC measure-ment circuit holds various inductance values preinstalled at different positions on the PCB.
Dependent on the unbiased capacitance value, the DUT varactor module is connected to the corresponding inductance value at a certain location on the PCB to obtain a resonance frequency close to 13.56 MHz. The inductance range preinstalled on the board ranges from
RF Source 13.56 MHz, 50Ω
1 nF 50 Ω
1 MΩ
Measurement tap 1
1.2µH 1.2µH
1 MΩ Measurement tap 2
DUT
Lres
Lfilter
Cfilter
Lfilter
Behlke HV switch
10µF 1.1 kV
(a)RLC measurement circuit with fast transient DC suppression in the measurement path.
0 50 100 150 200
−100
−50 0 50 100
Time / µs
Voltage/V
damped undamped
(b)ADS simulation results of the fast transient coupling into measurement tap 2 with and without filtering. A 1 kV step voltage is applied with a rise time of 1 µs.
Figure 3.16: Basic transient measurement circuit with filtering and simulation result com-parison between the unsuppressed and suppressed case.
44 nH to 1820 nH, resulting in an unbiased capacitance measurement range from 3100 pF to 76 pF.
To show the robustness ot the capacitance extraction, the measurement circuit is expanded with parasitics. A±5 % parameter variation is applied to all relevant components in the circuit. The dominant parasitics are ohmic losses in the metalization, filter coils, the resonant circuit and a parasitic inductance of the metal strip connecting to the inductance value taps.
The ohmic losses are modeled with 0.1Ωwhile the parasitic inductance is included in the parameter variation of the resonance inductance. A parasitic capacitance of the PCB to ground is introduced in the model. The capacitance is modeled with a value of 2 pF from the parallel plate capacitance equation, with a gap of the board to the grounded housing of 70 mm and an electrode area of 52 mm×300 mm. A simulation with the parameter variation is performed in Keysights ADS. The expanded transient equivalent circuit model and the results of the±5 % parameter variation simulation are depicted in figure 3.17.
The±5 % parameter variation in the circuit results in a relative error of the capacitance reading from the voltage envelope of maximum 6.6 %. By inverting the obtained curve, the RF voltage to capacitance transfer characteristic is obtained which enables an extraction of capacitance values from the RF envelope measurement. The measurement principle is performed on a thick film varactor and a circuit board integrated bulk ceramic disk varactor module in section 4.5 and section 5.2.1.
RF Source 13.56 MHz, 50Ω
1 nF 50 Ω
1 MΩ
Reference voltage measurement
1.2µH
0.1 Ω
1.2µH
0.1 Ω 2 pF
1 MΩ
LC circuit voltage measurement
DUT
69 nH
0.1 Ω Lfilter
Cfilter
Lfilter
Behlke HV switch
10µF 1.1 kV
(a)Transient characterization circuit with parasitic components.
0.5 1 1.5 2 2.5 3 3.5 4
0 1 2 3 4
Capacitance / nF
Voltageenvelopemagnitude/V VLC 5 % var.
(b)Lookup curve with a±5 % parameter variation for robustness examination.
Figure 3.17: Transient characterization circuit with parasitic components andV(C)lookup curve with±5 % parameter variation obtained at the LC circuit voltage measurement tap.
High-Power Thick Film Varactors
The design of thick film varactors for high-power applications is driven by two sets of pa-rameters. The first set arises from the manufacturing process and technology and defines the physical properties of the dielectric material such as density, porosity, permittivity, elasticity, etc. Most of these parameters are based on literature reference values. Possible deviations are modeled during the design process. The second set of parameters is defined by the application and its requirements on the varactor. These parameters include for example capacitance, DC biasing voltage, RF voltage amplitude, current carrying capabilities, dissi-pated power, etc. and are set up by the outer dimensions of the varactor and its geometry.
Due to their accessibility during the design process, the second set of parameters is subject to change more frequently than the first set. Most of these parameters are correlated to each other not only in their set but also between sets. For example, an increased permittivity, due to a change in the sintering process, leads to a different unbiased capacitance value without a change in geometry of the varactor [49]. The sintering process, however, also affects the loss tangent of the material resulting in a change of required cooling surface [14].
In this work, both sets of parameters are targeted to obtain varactors suitable for applica-tion in matching circuits with power ratings up to 1 kW. The thick films are applied by screen-printing, a low cost, fast and accurate depositioning technique, see section 2.2.2. For metalization, LTCC and screen-printing compatibility is pivotal as well as solderability and electrical conductivity. These requirements limit the selection of a metalization paste to just a few Ag-based pastes. All thick film varactors presented in this work are vertically layered metal-insulator-metal (MIM) varactors. This kind of setup introduces several advantages in comparison to planar structures. The small electrode gaps and high electrode overlap regions result in high single varactor capacitance values. Additionally, the electrode setup shows a favorable field utilization in regard to the DC biasing field compared to planar structures.
4.1 High-Power Varactor Design Process and Implementation
This section presents, the design process for thick film varactors optimized for high-power operation. Compared to acoustically optimized thick film varactors, the acoustical behavior is not included in the design process but monitored and verified with accompanying
simulations. Thereby, necessary reference data is obtained to quantify the benefit-cost ratio of the more complex acoustically optimized high-power thick film varactors. In general, for the implementation of high-power thick film varactors, two design challenges occur. Due to their thin dielectric layer compared to bulk ceramic varactors, the RF voltage amplitude is in the range of the DC biasing voltage leading to self-tuning of the varactor by the RF voltage for a single MIM structure. A 1:10 ratio between RF and DC voltage is usually desired. In addition, the electrical breakdown field strength of the thick film is easily exceeded since DC and RF voltage are superimposed at the MIM structure. The second challenge is the large permittivity of the thick film resulting in small geometric dimensions for a single MIM structure to obtain the required capacitance value for the high-power application. The large cooling surface, is contradicting this design flow, but required to ensure a stable operating temperature of the varactor and avoid temperature induced self-tuning during high-power operation (see figure 2.9b). A possible solution to all of these partially contradicting design limitations is the strategy of serial stacking MIM structures to distribute RF energy among a larger area while keeping reasonably high overall capacitance values. In general, a single or uneven number of series connected MIM structure is an unfavorable setup, as the DC biasing potential requires an isolated connection point. Therefore, at least two series connected MIM structures, a MIM cell, form the basic varactor structure presented in this work. However, with increasing number of interconnected MIM cells, the complexity of the biasing circuit increases. More severe for the fast biasing scheme and motivating this work, the load capacitance increases, as the RF-wise serially stacked varactors are connected in parallel with respect to the DC source. As a compromise between complexity and power handling capabilities, a maximum serial connected stack of four MIM cells is presented in this work.
The designed varactors are monitored but not optimized in regard to their acoustic resonance locations in the impedance spectrum. An interfering resonance spike of the equivalent series resistance (ESR) of the varactor with the operational frequency of a high-power matching application causes significantly increased losses in the varactor and reduces its power handling capabilities severely, see figure 2.8. The designed varactors are developed for single frequency, high-power matching circuits utilized for plasma etching or depositioning processes. The required power ranges from a few W to 1 kW. The design flow, developed in this work for varactors capable of stably operating at these power levels, is depicted in figure 4.1.
Matching circuits, adapting the impedance of the plasma to the impedance of the RF generator, need to be capable of handling the occurring heavy currents and high voltages in the stationary case and during a change in load when the plasma is ignited or extinguished.
The plasma, as a highly non-linear load, reflects harmonics of the excitation frequency back into the matching circuit superimposing with the RF voltage of the generator, resulting in additional voltage and current stresses at the components of the matching circuit [70].
Therefore, an exact model of the L-match circuit, including parasitics, is set up in Keysights ADS to estimate the expectable voltage and current stresses and the dissipated power of a thick film varactor substituting a state of the art vacuum capacitor. The utilized circuit
BST layer thickness Required cooling surface
Power rating
Required unbiased capacitance value
Electrode overlap Varactor pairs in series
Design optimization Self-resonance
frequency
Manufacturing tolerances
Estimation of acoustic resonances
Figure 4.1: Design flow for high-power optimized thick film varactors.
is the same one used for large-signal characterization and depicted in figure 3.13. For the application of a thick film varactor, two possible positions in the L-match circuit are viable.
EitherCVac1 orCVac2 can be substituted with a thick film varactor for testing. In a final application, both varactors are supposed to be substituted. For characterization, the position ofCVac1in the circuit is best suited for a substitution by a high-power thick film varactor for two reasons:
• The required capacitance value in this position is well in range of a thick film varactor without the need for serial stacks including more than three varactor cells. For three varactor cells the DC biasing network can be implemented on-substrate. For higher stack numbers this is not possible anymore, due to space limitations on the carrier substrate.
• The shunt branch supplies a direct path to DC/RF ground. As a result, the DC biasing network for the varactor can be simplified.
To design the high-power thick film varactor, the differential voltage and current through the vacuum varactorCVac1at a certain power level serves as the foundation of the design process.
For this, a load is chosen according to an inductively coupled plasma with the impedance in the ignited state [70, 71]. An input impedance ofZ∗M into the load of(1.86+3.02i)Ω and (2.92+0.85i)Ω is presented to the matching circuit for power levels up to 400 W, see figure 3.13. For power levels up to 1 kW a load impedance of (3.7+14.9i)Ω is set up. The different loading impedances are necessary, due to the temperature dependent unbiased capacitance value and the limited tuning range of thick film varactors. With an increasing power level, the temperature in each component of the circuit is increased as a consequence of the increase of dissipated power. The vacuum varactors provide for a stable base capacitance value and a tunability of up to 90 % independent of temperature. BST
based thick film varactors have a temperature dependent unbiased capacitance value and a tunability of up to 40 % at room temperature [10, 14]. Both values reduce with increasing temperature (see section 2.1.1). As a result, the load impedance has to be adapted for the changed component value of the thick film varactor.
The model depicted in figure 3.13 is set up in Keysights ADS to obtain reference data for the occurring voltage and current stresses in the circuit. First, a 1-port S-parameter simulation of the circuit is set up to adjust the matching for a certain load. To find the exact values forCVac1andCVac2,S11 is evaluated. A reflection|S11| ≤ −20dB is assumed to be sufficient. For a given load impedance, the circuit is manually adjusted to meet the matching criteria. This is necessary, due to the large difference from the generator impedance to the load impedance, resulting in a narrow-band matching. For the application, this means that the zero-bias capacitance has to be reproducible, in regard to the varactor fabrication process. In biased state, the capacitance has to be either reproducible for each biasing voltage as well and remain static by accurately controlling the temperature or readjustable to compensate thermal detunage. With the given setup, the voltage and current stresses at CVac1are simulated for different power levels. For that, both varactorsCVac1andCVac2are assumed to be of constant capacitance. During development, the parameters ofCVac1are further adapted to the parameters assumed for a thick film varactor. While adapting the varactor parameters, matching has to be closely monitored as it is affected by the changes.
In order to estimate the dissipated power of the thick film varactor, a quality factor of 100 is added to it, taken from [14]. The simulation results for different load impedances are shown in table 4.1. With increasing input power level and decreasing capacitanceCVac1, simulating the increase in temperature of a thick film varactor, the loading of the varactor changes to less stressful states. Equilibrium operation points arise. To account for that, not only the evaluation of the input power level is taken as a benchmark value of the varactor but its exact loading condition withVRMS,IRMSandPdiss.
The voltage stresses indicate, that for power levels up to 200 W, one varactor cell is sufficient to reduce the voltage amplitude per MIM structure to 100 V. Then, with a biasing voltage of 200 V for MIM thick film varactors given in [10], a DC to RF ratio of minimum 2:1 can be achieved. Commonly, higher ratios are of course desired. However a ratio of 10:1 is hard to achieve with the given technology and for the intended application unnecessary, as prevented self-tuning of the varactors suppresses harmonics, which are introduced anyway by the highly non-linear plasma. For higher power levels, series stacks of two and three varactor cells are required to keep the same ratio. The simulated dissipated power values are used to set up a thermal simulation of the varactor to estimate the required cooling surface and therefore electrode overlap area of the varactor.
The thermal simulation is performed in COMSOL Multiphysics and combines the transfer of heat in a solid with the laminar flow of a fluid/gas for the stationary case, meaning in equilibrium state of heat inflow and outflow. It is possible to not only estimate the temperature profile in the varactor itself but also take the cooling effect of an air flow due to a fan into account. Additional cooling with a heat sink on the varactor is also considered