7.1. ESTABLISHING THE QUIESCENT OPERATING POINT
The Meaning of Bias. In a vacuum-tube amplifier, bias refers to the d-c voltage applied to the grid of the tube to establish its operating point on the dynamic charac-teristic curve. In a transistor amplifier, bias can be considered to be the direct current applied to the input terminal of the transistor (base or emitter) to establish an operating point on the load line of the output characteristic curve.
In these discussions we refer to the output (collector) current and the output voltage (VCE or VCB) as the bias point. When setting the bias, we are interested in maintaining control of the collector current rather than the base or emitter current;
hence our interest is in the stability of the bias point and not the actual bias current.
For vacuum-tube amplifiers it is relatively simple to draw a load line on a set of common-cathode characteristic curves (IB vs. VB), select an operating point, and establish it by either a fixed grid bias supply voltage or a resistor in series with the cathode. A similar approach is possible with transistors: One can draw a load line on a set of common -emitter characteristic curves (I C vs. V CE), select a desirable value of quiescent collector current, and calculate the proper value of base resistance
(a)
+
~vcc
Figure 7.1
105
hIE
Bo---JV
-
Ie~~~--~~----oC
E E
Figure 7.2
to establish the required base current. This approach leads logically to a circuit like that in Fig. 7.1. The base resistance, R1, is chosen by assuming that the base-to-emitter voltage (VBE) of the transistor is zero: i.e., Rl
=
Vee! lB. Designs of this type have both simplicity and a charming element of unpredictability. If Rl (and hence, IB ) is fixed, there is nothing to prevent Ie from varying in accordance with the current gain, hFE' of the transistor. This type of biasing is very roughly analogous to fixed-bias vacuum-tube amplifiers; but while there are many advan-tageous applications for fixed-bias vacuum-tube amplifiers, a similarly biased transistor stage should not be used in any application. Generally, a graphical approach to bias network design is oflittle use in transistor circuitry for the follow-ing reasons: (1) There is a wide variation in common-emitter characteristics between devices; (2) the characteristics of each device vary widely with temperature; and (3) the common-base characteristics do not quite describe the transistor in a practical circuit. It is more useful to do an analytical bias design, using equivalent circuits for both the transistor and the external circuit.Transistor Equivalent Circuit. The equivalent circuit used in this discussion (Fig. 7.2) is an approximation of the general hybrid two-port representation of the transistor. The parameters shown in this circuit are the common-emitter d-c h parameters.
The approximation to this circuit is shown in Fig. 7.3. The quantity hOE can be neglected because it will generally be quite small compared to any external con-ductance connected between the collector and emitter terminals. Generally, hRE is negligible at low frequencies, and hIE is replaced by the voltage drop VBE across a diode to represent the base-emitter input characteristic.
External Circuit. Any network connected external to the three terminals of the transistor can be reduced to a T equivalent as in Fig. 7.4. As an illustration of this, take the general bias circuit of Fig. 7.S and reduce it to the T network of Fig.
7.4. If these two circuits are to be equivalent, then we can apply Thevenin's
B O---~P----:-t--t
VEE
--.l
E
~---oC
Figure 7.3
Transistor Biasing 107
theorem to each pair of terminals. Considering only the external circuit, the resistance between the base and emitter terminals with all external voltage sources reduced to zero is
Between base and collector terminals,
and between emitter and collector,
RE
+
Rc = R2+
R3+
(R4+
R5)(R6+
R7 )R4
+
R5+
R6+
R7 Solving Eqs. (1), (2), and (3) simultaneously,RE
=
R2+
R7(R4+
R 5) R4+
R5+
R6+
R7 R R R6(R4+
R 5)c
=
3+
--....:....:...--=----'"'--R4+
R5+
R6+
R7and RB
=
Rl+
RsR7R4
+
R5+
R6+
R7Examining each pair of terminals for open-circuit voltages, we find that
T7' T7 R7
"BB
=
"ccR4
+
R5+
R6+
R7and V; ' V; R6
+
R7CC
=
CCR4
+
R5+
R6+
R7(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8) The circuit of Fig. 7.5 is perfectly general in that the equivalent of any single-stage bias network can be obtained from Eqs. (4) through (8) by setting the appropriate resistors equal to zero or infinity.
co----~~---~
Re
+1
-=-Vce
RB VBB
BO---'~.----+--1III~_--+ +
-=-
VeeE o - - - " ' \
Figure 7.4 Figure 7.S
C ICQ
-
Rch;EIB _- V~c
B
....-
IB- VBEl E IE
~ RE Figure 7.6
SeHing the Bias. By combining the internal and external equivalent circuits as in Fig. 7.6, an expression for the bias-point collector current, IoQ, can be obtained.
From Fig. 7.6,
ICQ
=
hFEIB+
(1+
M'E)IoBoIB
=
VBB - VBE - IoBoSI+
hpE)RE RB+
(1+
hFE)RE Combining Eqs. (9) and (10),I M'E(Vjm - VBE)
+
(1+
hFE)IoBo(RB+
RE) OQ-- RB
+
(1+
hFE)RE(9) (10)
(11) Equation (11) by itself does not yield the necessary information to bias a transistor in any given application; there are too many variables which must be arbitrarily chosen. However, the apparently arbitrary choice of IOQ and RB or RE is often restricted by the particular application. For example, if a low-noise amplifier is desired, a value of IOQ would be chosen such that IOQ/hFB is at or near the optimum value of emitter current recommended by the data sheet for minimum noise figure.
RB would also be chosen such that it is large compared to the recommended optimum signal source resistance, so that it does not appreciably affect the source resistance. The problem is then to solve Eq. (11) for the necessary value of emitter resistance. But this is no small problem, since we would also like a value of emitter resistance that would keep IOQ within certain reasonable limits.
The parameters hpE, VBE, and lOBO are all extremely temperature-dependent, and we must investigate Eq. (11) to see what happens to IOQ at the highest and lowest operating-junction temperatures. Inspection of Eq. (11) shows that minimum IOQ will occur when VBE, RB, and RE are at a maximum and I CBO, hpE, and VIm are at a minimum. If minimum lOBO
=
0, then hFE=
hFE. Using overlines to indicate maximum (most positive) values and underlines to indicate minimum (most nega-tive) values,I > hFE(YBB - VBE) _OQ = RB
+
RE(1+
hFE)This condition generally occurs at the lowest junction temperature.
(12)
Transistor Biasing 109
Similar reasoning shows that maximum IOQ occurs with minimum VBE and RE and with maximum lOBo, ME, V~B' and R B. Assuming ME approaches infinity as a maximum,
I
<Vim -
YBE+
lOBo(RB+
BE)OQ= BE (13)
This condition generally occurs at the highest junction temperature. Notice that the sign convention of these equations is correct for NPN transistors. The varia-tions in RB, RE, and VBB are due to resistance and power-supply tolerances and are of concern where such circuits are to be mass-produced.
If IOQ is to be held within the bounds of a given lOQ and lOQ, Eqs. (12) and (13) may be combined to specify an RE .
RE > bFE[ VBE(l
+
C) - YBE(l - D)+
lOB;RB(l - D)]+
loQRB(l+
C) - llFE(1oQ - IOBo)(1 - B)(l - D) -loQ(l+
llFE)(1+
A)(l+
C) (14)where RE
=
RE(1+
A) (15)and
BE = RE(1 - B)
VBB
=
VBB(l+
C)!:im
= VSB(l - D)(16) (17) (18) A and C are the tolerance limits on RE and Vim at the highest ambient temperature, and Band D are the limits at the lowest temperature. It is interesting to note that for Eq. (14) to have any meaning, the denominator must be positive and greater than zero. This imposes the condition
- (1
+
A)(1+
C) ~ 1 \-IOQ> (1 _ B)(1 _ D) ~
+
bF~}loQ+
lOBO (19) Equation (19) gives the minimum variation within which IOQ can be held under specified temperature extremes and resistance tolerances. This provides a quick check on whether a given set of limits on I CQ is possible, but says nothing about the practicality of such limits.7.2. HEAT DISSIPATION
Two thermal requirements must be met for satisfactory transistor operation:
1. The greatest instantaneous heat released at the junction must flow through the thermal impedance to the highest ambient temperature ever encountered without raising the junction above its maximum rated temperature. In other words, for Fig. 7.7,
Tjunction(max)
=
Tambient(max)+
D.TJ_A(max)2. The circuit must be stabilized against thermal runaway.
The instantaneous power released at the junction depends upon the instantaneous
CHJ
Figure 7.7
values of ia, VaE, iE, and VEE. For the general case, it consists of a steady-state component PJ and a time-varying component pJ(r). The lowest frequency present in the electrical signal will usually be the fundamental frequency of the Fourier expansion of pJ( r).
(20) In many designs the transistor carries only d-c and/or audio-frequency signals, and the power-transient peaks do not exceed about one-tenth second. From Sec. 4.4, since a conservative design results from taking CHJ
=
0, a good rule of thumb for transistors operating within these limits is(21) This expression would apply to the power stages of most audio amplifiers. It is also useful for estimating the peak tJ encountered in voltage-regulator designs.
For the latter purpose, PJ(marc) is taken to be the maximum steady-state Vasla product to be met in normal operation, while pJlpeak) is the peak instantaneous VaEia product that might be imposed by a transient condition. For the estimate to be conservative, the transistor case temperature must not change appreciably during the transient.
7.3. THERMAL STABILITY
Thermal Runaway. The second requirement for satisfactory operation con-cerns thermal stability. A rise in junction temperature alters the transistor param-eters in a direction that increases collector current. This increased current, in turn, may cause increased dissipation and higher junction temperature. If a transistor is to avoid thermal runaway, the rate at which heat released at the junction increases with a rise in junction temperature must not exceed the rate at which the amount of power which can be dissipated changes as the temperature changes. We may derive this criterion in the following way:
Thermal runaway consists of a repetition of three physical processes:
1. A change in ia results in a change in pJ(released).
2. A change in pJ(releasecf) results in a change in tJ.
3. A change in tJ results in a change in ia.
Each process may be considered as a black box defined by an input, an output, and a transfer function. This is diagrammed in Fig. 7.8.
Transistor Biasing 111
I ~:~ I ~~~ _______ A_P~'I
________ _ Figure 7.8Ifthe loop gain around this network is unity or greater at any frequency, that is, if IliCl !ltJ2 !lpJ3 > 1 (22) 1ltJ1 !lpJ2 !lic3 =
then thermal runaway is possible.
It will be convenient to evaluate each term of Eq. (22) as a derivative, and write the stability criterion as
dicl dtJ2 dpJ3
<
1dtJ1 dpJ2 diC3 (23)
Equations (22) and (23) assume that the transistor is not subject to thermal feedback from another heat source dependent upon the transistor currents:
e.g., two transistors in Darlington connection mounted upon the same heat sink. For these cases, Fig. 7.7 is no longer sufficient. The expression for (!ltJ2/ !lPJ2)(!lPJ3/i!lc3) becomes quite complicated and will not be presented here.
Approximations which circumvent this problem can usually be made for individual cases.
At any instant in its operation, the transistor must be in one of three conditions:
1. The transistor is ON and is not in saturation: i.e., the emitter diode is forward-biased, the collector diode is reverse-biased, and transistor action is taking place.
2. The transistor is ON and is in saturation: i.e., the emitter and collector diodes are both forward-biased.
3. The transistor is OFF: i.e., the collector diode is reverse-biased, the emitter diode is reverse-biased or unbiased, and no appreciable transistor action is occurring.
Thermal stability is of importance only in the first and, occasionally, the last cases.
Before discussing the application of Eq. (22), it will be helpful to examine in detail the form of its constituent derivatives.
Description of dtJ2/ dpJ2. Since tJ is a function of both pJ and the definite inte-gral of pJ with respect to time, dtJ2/ dpJ2 will also contain time-dependent terms.
In other words, at any instant of time, T
=
X,dtJ2 / dtJ2/ dT
dpJ2 r=:C
=
dpJ2/ dT (24)If the thermal impedance can be considered to be purely resistive, these circuitry external to it may almost always be reduced to one of the three-terminal networks shown in Figs. 7.9 and 7.10. These circuits are simply extensions of the network of Fig. 7.4.
ZBB, Zce, and K are used principally to describe active external circuit elements linking ic to iB: e.g., amplifier feedback loops. If the stage is isolated or if only passive elements are present, these terms may vanish.
These network parameters strongly influence the thermal stability of the stage.
If the transistor is directly affected by active elements in the external circuitry-as for example, a stage in a direct-coupled amplifier with an overall feedback loop-then the parameters of Figs. 7.9 and 7.10 may become both complex and negative.
Such a feedback loop may keep the stage thermally stable until an overload else-where in the amplifier opens the loop. Then the sudden shift of values may cause quick runaway.
The choice between Figs. 7.9 and 7.10 depends upon the base supply impedance.
For a low impedance, Fig. 7.9 is usually preferred; for a high impedance, Fig. 7.10 may be more convenient. When the network representation of Fig. 7.9 is feasible, diCl/dtJl may be evaluated in a convenient and useful form for an ON transistor by separating the circuit elements as shown in Fig. 7.11.
ie Z zeeiB Vee
Transistor Biasing 113
Figure 7.11
In Fig. 7.11, the entire circuit external to the transistor is represented on the right of the dashed line as an equivalent-T network: three impedances, ZE, Zo, and ZB, and four supply voltages, V~o, V~B' ZooiB' and ZBBio. On the left is an equivalent circuit for the transistor itself, in which the principal temperature-sensitive param-eters have been isolated. The basic equations are:
io
=
hFBiE+
lOBo (27)iB
+
iE+
io=
0 (28)VD = iE(ZE
+
rE) - iB(ZB+
rE)+
VEB+
ZBBiO (29) . hFB(VD - VEB)+
10Bo(ZB+
rE+
ZE+
rE) (30) 10 = (1+
hFB)(ZB+
rB)+
ZE+
rE+
hFBZBB(31) where S, the current stability factor, is defined by
S = ~ _ ZB
+
rB+
ZE+
rE . (32)- MOBO - (1
+
hFB)(ZB+
rE)+
ZE+
rE+
hFBZBBThe network in Fig. 7.10 may also be used to derive diod dtJl. The circuit is shown in Fig. 7.12, and the basic equations are:
io
=
hFBiE+
lOBoio
+
iB+
iE = 0 IBB+
Kio=
iB+
iZBVD = iE(rE
+
ZE)+
ZBiZB - iBrB(33) (34) (35) (36)
Figure 7.12
and . hFB(VD - ZslBB)
+
ICBO(ZB+
rB+
ZE+
rE) IC=
(1+
hFB)(ZB+
rB)+
ZBKMB+
ZE+
rfg Then,diCl S (dI CBO . dhFB9
- = + I E
-dtJ1 dtJ dtJ
[ ~ J
+
(1+
hpB)(ZB+
rB)+
ZBKM'B+
ZE+
ri;where
s
= dic _ ZB+
rB+
ZE+
rJ;- dIcBO - (1
+
hFB)(ZB+
rB)+
ZBKhpB+
ZE+
ri;If the base is driven from a constant-current source (i.e., if ZB
=
00), 1S = 1
+
hFB(l+
K)and dim
=
s(dICBO+
iE dhFB)dtJ1 dtJ dtJ
-
iZB(37)
(38) (39)
(40)
(41) Simplifying Assumptions. At the expense of a conservative design, several simplifying assumptions may be made:
1. At high junction temperatures,
(42) A conservative design results when this substitution is made in the numer-ator of the fraction in the first pair of brackets in Eqs. (31) and (38). It may also be possible to assume
and
hpBZBB - -ZBB MBZBK- -ZsK without serious loss of accuracy.
(43) (44)
Transistor Biasing 11 5
2. lOBo consists of at least two components: an ohmic leakage between collector and base, and the diode saturation current. For a reasonably clean junction, the saturation current usually dominates at high temperatures, and over a small !:::..tJ can be approximated by
lOBO ~ Nf.(Bt} (45)
dloBo ~ Bl
~= OBO (46)
B
=
ln2!:::..To (47)
where !:::..To is the number of centigrade degrees rise in junction required for lOBo to double. !:::..To is a complex function of temperature, but for silicon transistors operating near their upper temperature limits, !:::..To ~ 10 Co. If lOBo doubles every 10 CO rise, then
dloBo _ dtJ - . 006931 OBO (48) For germanium transistors, To ~ 14 Co, and
dloBo ~ 0.04591oBo
dtJ (49)
These approximations must be used with some caution, since surface states at the junction can produce erratic lOBO at elevated temperatures. Also, lOBO may be strongly dependent on VOB at voltages near avalanche break-down.
3. Since the first pairs of brackets in Eqs (31) and (38) enclose negative quantities, Idim /dtJ11 maximizes for an NPN transistor when the sum in the second pair of brackets reaches its most negative value. Theoretical considerations of the transistor suggest that
ddVD
~
- 0.0025 volt/COtJ (50)
For a PNP device, the sign of this quantity is positive. The two other quantities in the second brackets are often either of opposing sign or so small that they can safely be ignored.
4. The conservative minimum limit of
rJ:
is, of course, zero. (The evaluation of r~ and of dhpB/ dtJ will be discussed at the end of this chapter.)Thus, for NPN silicon transistors, Eq. (38) may be reduced to
~: =
S~.069310BO +
iE ddt;j+
(1+
hpB)(ZB+
0.0025 rs)+
ZE+
hpBZBB (51) Equation (37) becomesdiol ~ . dhpB) 0.0025
- d tJ1
=
S 0.06931oBo+
I E -d tJ+
(1+
h* )(Z FB B+
rB ')+
Z E+
KZsh* FB (52)Notice that Eq. (38) differs from Eq. (31) only in that the quantity KZ has been substituted for ZBB. To avoid duplication, the derivations which follow will be based only on Eq. (31). The corresponding results from Eq. (38) may be obtained by replacing ZBB with KZB. Also, the equations will show only the constants for NPN silicon transistors.
dPJ3/ die3 for an ON Transistor. The power dissipated in an ON transistor can be found from Fig. 7.9 or 7.10:
PJ
=
ie(Vce+
iBZee - ieZe+
iEZE)+
VBEiB (53)dPJ3 TT' Z ~ diB .~ 2Z· Z ~ . diE) . dVBE diB -d. = vee
+
ee Ie-d.+
lB - ele+
E IE+
Ie-d·+
lB-d.+
VBE-.le3 Ie Ie Ie die
(54) Substituting,
dpJ3 _
v:'
ee+
VBE-d. diBdie3 Ie
- Ie 2Ze - Zee -
. l (
h1 pE+ -. -
diB) die ZE (55) At the high junction temperatures which aggravate runaway, current gains are usually large, andIf no inductance is present in Ze or ZE, then for the NPN case dpJ3 < V,'
die3 = ee This is a very useful worst case approximation.
(56)
(57)
Complex Impedances. Complex electrical and thermal impedances can strongly affect thermal stability. Figure 7.13 gives two such examples. Both circuits may be quite stable if the electrical reactances are ignored. But it is intuitively obvious that if L is made large enough in the first circuit, the rate at which iB can change with time will become so slow that the transistor could run
+ +
c
(a)
(b)Figure 7.13
Transistor Biasing 117
away in the meanwhile. Similarly, as C becomes infinite in the second circuit, ZE approaches zero and S may become large enough for instability. The fact that runaway does not occur instantaneously for small values of L or C is due, in part, to the complex nature of the thermal impedance: as the rate of change of PJ with time increases, D.tJ2/ D.pJ2 usually decreases.
It has been customary for both the literature and the design engineer to ignore these reactive effects. The temptation is strong: an exact analysis is virtually impossible. The success of this philosophy may have resulted from three things:
(1) A design which is conservative on the basis of a resistive analysis alone is usually safe from reactive troubles; (2) a fast thermal runaway may not be recognized for what it is; and (3) reactive thermal runaways are sometimes oscillatory, and the blame gets placed on an unknown electrical feedback path. As transistor circuit design becomes more sophisticated, these problems may become more serious.
Quiescent Stability. The first requirement for any circuit is that thermal run-away will not occur at an infinitely slow rate. Equation (22) must be satisfied for the zero-frequency, or quiescent, condition. This is a simple mode to evaluate, since all capacitive and inductive reactances are effectively open and short circuits, respectively. The thermal circuit has the simplicity of Fig. 7.7, and if the network of Fig. 7.9 were used with a silicon transistor, Eq. (22) would become approximately
l>
Vec - 2IcQ(Rc+
RE) OT (1+
hFB)(RB+
rfJ)+
RE - ZBB[(RB
+
rB+ RE)~.0693IcBO +
IEQd~;;) +
0.0025 J (58)where ICQ and IEQ are quiescent currents.
If this expression is solved for RE , a rather unmanageable quadratic results. But if ZE is neglected in Eq. (56), then
OT (Vec - 2IcQRc)
~RB +
rB) 0.0693IcBo+
IEQd~~B +
0.0025J+
ZBB - (1+
hFB)(RB+
rB) RE>
---;---,--::-.---, t
dhl'B)1 - OT (Vcc - 2IcQRc) ~.0693IcBo
+
IEQ dtJ (59) Of course, these inequalities-and the ones which follow-must be evaluated for the peak junction temperature that might be reached during any signal conditions1 - OT (Vcc - 2IcQRc) ~.0693IcBo