BURROUGHS B 5500
SIMULTANEOUS OPERATIONS
SIMULTANEOUS OPERATIONS
The Burroughs B 5500 Information Processing system can concurrently execute:
• One or two machine instructions (one per Processor); and
• Up to four input-output operations, one for each available B 5283 I/O Channel.
Because each of the core storage Memory Modules has its own independent ad-dressing and read/write circuitry, simultaneous memory accesses are possible. The max-imum number of truly simultaneous accesses to core memory in a fully-expanded B 5500 system is six: one access by each of the two Processors and one access by each of the four I/O Channels. Six interleaved (not simultaneous) accesses to the same Memory Module are also permitted, although no more than two of these accesses can result from magnetic tape operations.
The B 5500 Processor initiates all peripheral input-output operations by sending a 48-bit I/O Descriptor to the I/O control unit. Normally the Processor is then free to per-form its operations, unaffecting and unaffected by the concurrent peripheral operations. The Processor's performance is delayed only when it accesses a Memory Module that is already being simultaneously accessed by another Processor or I/O Channel. Since data is transferred to and from the Memory Modules one word at a time, and since the memory cycle time per word is either four or six microseconds (for the B 461 and B 460 Modules, respectively), the Processor will normally be delayed only a minimal amount of time while awaiting access to a "busy" Memory Module.
Each I/O Channel is totally dedicated to its assigned input-output task once it has been selected by the I/O control unit. The line printers and data communications terminals have their own internal buffers, and therefore the I/O Channels are released immediately after loading or emptying these buffers. Up to four input-output operations can be performed simultaneously, one per installed I/O Channel, since each I/O Channel functions independently of the others.
Jnput-output data transfers utilize the accessed Memory Module only during each 48-bit, single-word transfer; the memory access time per word is either four or six micro-seconds, depending on whether the B 461 or B 460 Memory Modules are used. The number of memory accesses required for each input-output operation, or, alternatively, the time required for memory accesses as a percentage of the total time for the I/O operation, is specified in the report sections describing the individual B 5500 peripheral units.
© 1965 AUERBACH Corporation and AUERBACH Info, Inc. 10/65
BURROUGHS B 5500
INSTRUCTION LIST
~
AUERBACHE D P
REPORTS
.1
INSTRUCTION LIST
WORD MODE
Each Word Mode syllable is 12 bits long and may be one of the following four types, as designated by the two low-order bits.
the descriptor address, and bring the word at this address to A.
• If (A) is a Program Descriptor, enter the addressed subroutine •
• 11 Literal (bit code 00) • 13 Descriptor Call (bit code 11) The ten high-order bits are placed in A as a positive
integer.
The ten high-order bits are added to (R); the word at this address is brought to A. Then:
.12 Operand Call (bit code 10) • If (A) is an operand, construct a descriptor of that operand and place it in A.
The ten high order-bits are added to (R); the word
at this address is brought to A. Then: • If (A) is a Data Descriptor whose size field is zero, no further action occurs.
• If (A) is an operand, no further action occurs.
• If (A) is a Data Descriptor whose size field is zero, bring the word at the descriptor addres s to A.
• If (A) is a Data Descriptor whose size field is non-zero, add the ten low-order bits of (B) to the descriptor address.
• If (A) is a Data Descriptor whose size field is non-zero, add the ten low-order bits of (B) to
• If (A) is a Program Descriptor, enter the addressed subroutine.
OPERATOR
10/65 ADD SUB MUL DIV IDV RDV DLA DL8 DLM DLD
LND LOR LQV LNG GTR LSS LEQ EQL NEQ GEQ
. Arithmetic (B)
+
(A)-+B (B) - (A)-+B (B) x (A)-+B• 14 Operators (bit code 01)
OPERATION
(B) :- (A) ~ B; quotient is normalized and rounded.
Normalize (A) and (B); then (B) ;. (A) ~ B
NormSllize (A) and (B); divide (B) by (A); store remainder in B.
(53 & 84)
+
(A & B) ~ A & B; i. e., double length add.(53 & 54) - (A & B) ~A & B (53 & 54) x (A & B) ~A & B (53 & 54) ;. (A & B) ~ A & B
AND: If 1 appears in corresponding bit position of both A and B,retain the 1 in B; otherwise place a 0 in B. Mark A empty.
OR: If 1 appears in corresponding bit pOSitions of either A or B, place a 1 in B; otherwise place a 0 in B. Mark A empty.
EQUIVALENCE: If corresponding bits of A and B are equal, place a 1 in B; otherwise place a
o
in B. Mark A empty.NEGATE: Change all zeros to ones and all ones to zeros in Register A, except flag bit is unaltered.
If (B) > (A), 1 -+ B; otherwise 0 ~ B.
If (B) <' (A), 1 -+ B; otherwise 0 ~ B.
If (B):::;; (A), 1 -+ B; otherwise 0 ~ B.
If (B)= (A), 1 -+ B; otherwise 0 ---»-B.
If (B)¥- (A), 1 ~ B; otherwise 0 ~ B.
If (B);::(A), 1 -+ B; otherwise 0 -+ B.
A
AUERBACH
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INSTRUCTION LIST
.14 Word Mode Operators (Contd.) OPERATOR
nnFCE nnFCL nnTFB nnDIA nnDffi MDS MOP TOP SSN SSP CHS FBS LLL
XCH DUP DEL SSF
SND STD IBN ISD CND
cm
Is1S0 CTC CTF FTC FTF
OPERATION Logic (Contd.)
Compare nn bits of (A) to nn bits of (B); If equal, 1-7A; otherwise 0-7A.
Compare nn bits of (A) to nn bits of (B); If (B) < (A), I-?A; otherwise 0 ---3!0A.
Copy nn bits from A to B.
nn-7 G & H unless nn
= o.
nn-7 K & V unless nn
= o.
Set flag bit of (A) to 1, making (A) a descriptor.
Set flag bit of (A) to 0, making (A) an operand.
If flag bit of (A) is 0, 1-7A; otherwise O-?A.
Set sign of (A) to 1.
Set sign of (A) to
o.
Change sign of (A).
Search for word with flag bit on (Le. , descriptor) beginning at address in A.
Place in A the address of first descriptor found.
Compare a field in (A) to a list of words beginning at the address in B, placing each list word in (B) for the test. When (A) is < (B), place the address of the word in B into A.
-Data Transfers
Exchange (A) and (B).
Adjust stack until A is empty and B is full; duplicate (B) in A.
Delete the top word of stack; L e., (A).
If two low-order bits of (A) are zeros, store (F) in B; if they are ones, store (B) in S; if only the low-order bit is zero, set subprogram switch and store (B) in F; if only the low-order bit is one, store (8) in B.
In the following store operators, if A contains a descriptor, (B) is stored in the address it specifies. If A contains an operand, (B) is stored at the address formed by modifying (A) by (R) or (F).
Store (B); mark A empty, but retain (B).
Store (B); mark A and B empty.
Convert (B) to an integer and store; mark A empty, but retain (B).
Convert (B) to an integer and store; mark A and B empty.
If low-order bit of (A) is 1, proceed as in ISN, above; otherwise proceed as in SND, above.
If low-order bit of (A) is 1, proceed as in lSD, above; otherwise proceed as in STD, above.
Store a G- and H-specified field from (A), with a length of Is, in the low order bits of A, and set rest of (A) to zero.
Store the 15 low-order bits of (A) in the 15 low-order bits of (B).
Store the 15 low-order bits of (A) in bits 16 through 30 of (B).
Store bits 16 through 30 of (A) in the 15 low-order bits of (B).
Store bits 16 through 30 of (A) in bits 16 through 30 of (B).
© 1965 AUERBACH Corporation and AUERBACH Info, Inc.
203: 121. 141
10/65
• 14 Word Mode Operators (Contd.) OPERATOR
BFW BBW BFC BBC CFD CFN CBD CBN
MKS XlT RTN BRT CMN
PRL COC CDC COM LOD INX TUS TIO
no
HP2IPI IP2 ITI RTR lOR
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OPERATION Branching
In all branching operations, if (A) is an operand it specifies number of syllables to be jumped. If (A) is a descriptor, it specifies destination address.
Branch forward unconditionally.
Branch backward unconditionally.
Branch forward unless low-order bit of (B) is 1 (set by compare operations).
Branch backward unless low-order bit of (B) is 1 (set by compare operations).
If a G- and H-specified.field of (B) is not zero, mark B empty, and proceed as in BFW, above.
If G- and H-specified field of (B) is not zero, proceed as in BFW, above.
If a G- and H-specified field of (B) is not zero, mark B empty, and proceed as in BBW, above.
If a G- and H-specified field of (B) is not zero, proceed as in BBW, above.
Subroutine Operators
MARK STACK: Push down (A) and (B) into stack. Construct Mark Stack control word containing (F) and (R), store it in stack, and copy its stack address into F.
EXIT: (A subroutine return in the Word Mode) Reset contents of C, L, G, H, K, V. R. and F from the Return and Mark Stack control words. Mark A and B empty.
RETURN: (A subroutine return in the Character Mode) Adjust stack until A is full and B is empty. Reset contents of C, L, G, H, K, V, R, and F from the Return and Mark Stack control words.
BRANCH RETURN: If presence bit is 1, set S and C from (A); restore R and F from Mark Stack control word; mark A and B empty.
ENTER CHARACTER MODE IN-LINE: Push (A) and (B) into stack. Construct Return control word containing (C) and (L), store it in stack, and copy its stack address into F. Store the word below the Return control word in S, and set sub-program and Character-Mode switches.
Miscellaneous Operators PROGRAM RELEASE
CONSTRUCT OPERAND CALL CONSTRUCT DESCRIPTOR CALL
COMMUNICATION: Store (A) in a specific location and set communication bit in Interrupt register.
LOAD OPERA TOR
INDEX: Add 15 low-order bits of (B) to (A).
Store in A a peripheral unit's status word, and set a bit indicating each unit's readiness or non-readiness.
Store in A an integer indicating the lowest-numbered currently-available 1/0 Channel. Store a zero if all Channels are busy.
Control State Operators
Note: The following operators may be used only when the Processor is in the Control State as a result of an interrupt. All the preceding Normal State operators may also be used in the Control State.
Cause Processor 2 to store its registers in the stack and halt.
Store (A) in a specific location; send an Initiate 1/0 signal to Central Control for selection of an 1/0 Channel.
Set Processor 1 's registers from fixed storage location and exit from Control State.
Store' (A) in a specifiC location and activate Processor 2.
Interrogate the Interrupt Register; if any interrupt bit is on, transfer control to the corresponding storage location.
Timer setting~A.
1/0 RELEASE: Set presence bit to 1 in location formed by modifying (A) by (R) or (F).
fA.
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INSTRUCTION LIST
.2 CHARACTER MODE
Each Character Mode syllable is a 12-bit operator consisting of a 6-bit repeat field and a 6-bit operation code. The following operators are available.
OPERATOR
(PC)-7DC, for nn successive characters.
(SC) -7DC, for nn successive characters.
Same as TRS, but transfer numeric bits only.
Same as TRS, but transfer zone bits only.
Replace with blanks all characters in a.field specified by S and K that are equal to or less than zerOB-. Terminate operation when a greater-than-zero character is encountered.
Skip Operators
Skip forward over nn source characters.
Skip backward over nn source characters.
Skip forward over nn destination characters.
Skip backward over nn destination characters.
Skip nn successive source bits.
Skip nn successive destination bits ..
Address Operators
Set source address: next 3 source chars ~M & G; 0 --7H.
Set destination address: next 3 destination chars ~S & K; 0--7V.
Set source address from a word in stack.
Set destination address from a word in stack.
Store source address in stack.
Store destination address in stack.
Store control address (contents of C & L) in stack.
© 1965 AUERBACH Corporotion ond AUERBACH Info, Inc.
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.2 CHARACTER MODE (Contd.)
.3
OPERATOR OPERATION
REPEAT OP. CODE
Jump Operators
nn JFW Jump forward nn syllables.
nn JRV Jump backward nn syllables.
nn JFC Jump forward nn syllables unless T/F toggle
=
1.nn JRC Jump backward nn syllables unless T/F toggle
=
1.nn BNS Execute the following loop nn times.
-
ENS Identifies end of a program loop.nn JNS Jump forward nn syllables to a syllable following end of loop (ENS), do not count around loop.
nn JNC If T/F toggle
=
0, proceed as in JNS.Conversion Operators
nn OCV Convert 1 octal word in source string to nn decimal digits (8 max.) in destination string.
nn ICV Convert nn decimal digits (8 max.) in source string to 1-word octal integer in destination string.
Miscellaneous Operators nn SEC Set R (tally register) to nn.
nn INC Increment (R) by' nn; ignore overflow.
nn STC Store (R) in stack at location (F + nn).
nn BIS Set nn successive bits in destination string to 1.
nn Bm Set nn successive bits in destination string to zero.
nn CRF Use 'the 6 low-order bits of (F + nn) as repeat field for next syllable.
-
EXC Exit from Character Mode and re-enter Word Mode, resetting Registers C, L, G, H, K, V, S, F, and R from control words in the stack.-
CMX EXIT CHARACTER MODE IN-LINE (same as EXC, above, except that Registers C and L are not set).INSTRUCTION LIST NOMENCLA TURE
A: •••••••••••••• A register; top location in stack.
B: •••••••••••••• B register; second loca-tion in stack.
b: •••••••••••••• a bit used as a literal in repeat field of a Char-acter Mode syllable.
C: •••••••••••.•• C register.
DC: ••••••••••••. next character in the des-tination string.
DW: •••••••.••... next word in the desti-nation string.
F: •••••.•••••••• F register.
G: • • • • • • • • • • • • . . G register.
H: ••••••••••••.• H register.
K: • • • • • • • • • • • • • • K register.
L:" • • • • • • • • • • • • . • L register.
1: •••••••••••••• number of characters (in-cluded in operator syllable) . M: ••••••••••••.. M register.
nn: ••••••••••••• a 6-bit literal.
PC: ••••••••••••• next character in the pro-gram segment.
R: . . • • • . • . . • . . . . R register.
r: • • • • . • . • . • • • . . a character used as a literal.
S: • • • • • . • . • • • • . . S register.
s: • • • . • • . . . • • . number of bits to shift a result (included in operator syllable).
SC: • • • . • • • . . . • • . next character in the source string.
SW: • . • . • • • • . . . • . next word in the source string.
S3:} . . . • • • . . . the third and fourth
loca-S4: tions in the stack (core
storage locations addres-sed by the S register).
T/F: . . . • . . . • • • . • True/False toggle.
V: • • . . . • • . . • • . • • V register.
( ):. . . • • . • • • . . • • the contents of a register or location.
Note: The functions of all Processor registers are described in Paragraph 203:051. 24.
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