3.1 PRIVILEGED MODE
To inhibit interrupts or to access an area in memory known as protected memory, the processor must be placed in privileged mode. This mode is entered whenever an interrupt occurs.
3.1.1 Protected Memory
Protected memory is an area in main core storage that cannot be altered unless the processor is operating in privileged mode. The protected area includes at least the first 512 word locations (00000 through 007FF in hexadecimal). It can be expanded in modules of 512 words up to 16,384 words. The use of protected
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memory depends on' system requirements, but some areas are fixed in any C-8561A-2 Processor; these are listed in appendix D of this manual.
3.1.2 Entering Privileged Mode
Privileged mode is entered by the processor when a branch and set return link to protected area instruction is executed. This instruction (described in detail in section 4) is similar to the branch and set return link instruction used for sub-routine entry, but it branches the program to a fixed memory location in protected memory. The contents of this location are established in the initial program load operation; the word may branch the program back to the next instruction in the originating program, or it may be the entry point to a subroutine that handles all privileged mode operations, depending on the program system.
3.1.3 Exiting Privileged Mode
The Branch and Enable Protection instruction (described in detail in section 4) removes the processor from the privileged mode of operation.
3.2 INTERRUPTS
When an interrupt condition occurs, the contents of the instruction address counter (P register), the overflow indicator, and the condition code are stored in a fixed location of protected memory, and a new address is loaded into the instruction address counter from a second fixed location. The fixed locations have the following format:
WORD 1
I:EROS
1al
NEW lAC (P REG)
aJ
14
WORD 2
I :EROS
CI
0
I
T
I
OLD lAC (P REG)
aJ
5 6 7 8 9 14
Revised 30 June 1970 3-1
privileged mode and interrupts
Where C indicates condition code, 0 is the overflow indicator, and T is the timer interval specification bit (O=timer zero, 1 =timer one).
The address of each pair of fixed locations is determined by the type of interrupt. The machine enters the privileged mode when interrupted, and the next instruction to be executed is determined by the new instruction address. Three classes of interrupt can occur; program interrupt, memory parity interrupt, and interval timer interrupt. The conditions that cause these interrupts and the conditions that inhibit them are described in the following paragraphs.
3.2.1 Program Interrupt
A program interrupt occurs under any of the following conditions:
An invalid address is detected.
An invalid operation code is detected.
A direct control instruction is attempted with the processor in the non-privileged mode.
A write into protected memory is attempted with the processor in the non-privileged mode.
An invalid address is detected when a memory address exceeds the highest address in the implemented memory, or when a write to protected memory is attempted with the processor in the nonprivileged mode.
An invalid operation code is detected when bits 4 through 7 of the instruction word specify a code that is not defined by the C-8500 instruction set. A program interrupt cannot be inhibited.
3.2.2 Memory Parity Interrupt
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A memory parity interrupt occurs when a memory parity error occurs during a memory read initiated by the arithmetic logic and control unit. A memory parity interrupt cannot be inhibited.13.2.3 Interval Timer Interrupt
The timer interrupt can be inhibited by masking as described in paragraph 3.2.5. A timer interrupt occurs when a fixed time interval determined by the processor service unit elapses. The timer intervals available are 24 and 2.4 milliseconds.
3.2.4 Memory Interrupt Locations
When an interrupt occurs, machine conditions are stored in a fixed memory location. The instruction address counter content is stored in bits 14 through 31; the overflow indicator is stored in bit 8; the condition indicator is stored in bits 6 and 7; bit 9 is set to 1 when a timer interrupt is received from the 2.4 ms timer. For all other interrupts bit 9 is a O. Bits 0 through 5 and 10 through 13 normally contain O. The fixed locations determined by the classes of interrupt are shown in table 3-1.
3.2.5 Interrupt Priority and Masking Interrupt priorities are as follows:
Program interrupt - priority 1 Memory parity interrupt - priority 2 Timer interrupt - priority 3
Table 3-2 summarizes interrupt priorities and interrupt inhibit masking. Each interrupt is listed according to priority in its class.
3-2 Revised 30 June 1970
privileged mode and interrupts
Table 3-1. Memory Interrupt Locations.
CLASS LOCATION CONTENT
(hexadecimal)
Program AO New instruction address
A4 Previous instruction address, overflow
indicator, and condition indicator
Memory parity AS New instruction address
AC Previous instruction address, overflow
indicator, and condition indicator
Timer BO New instruction address
B4 Previous instruction address, overflow
indicator, and condition indicator
Revised 30 June 1970 3-3
Table 3-2. Interrupt Priority and Masking.
CLASS INTERRUPT MEMORY LOCATION PRIORITY MASK CONDITION
PREY NEW
Program Invalid address A4 AO 1A Cannot be masked
Illegal operation A4 AO 1A Cannot be masked
Direct control instruc- A4 AO 1A Cannot be masked
tions without privileged mode
Parity Memory parity error AC AS 2 Cannot be masked
on alcu read
Timer Timer zero (24 ms) B4 BO 3A *p register bit 16
masked and privi-leged mode enabled
Timer one (2.4 ms) B4 BO 3B *p register bit 1 7
masked
*Bits 16 and 17 of the P register (instruction address counter) contain the least significant bits of the instruction address.
These bits are not used for addressing purposes, and can be set and reset with corresponding 1 's and O's in the address field of a branch instruction.