DATA TRANSFER INSTRUCTIONS .1 Load Accumulator (IC)

operation repertoire

4.1 DATA TRANSFER INSTRUCTIONS .1 Load Accumulator (IC)

The content of the word(s) whose leftmost byte is specified by the effective address is inserted into the accumulator specified in the M field.

The M field is set as follows:

01 - accumulator A 10 - accumulator B 11 - accumulator D

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the content of the entire accumulator is compared to zero, and the condition indicator is set as follows:

1 - less than zero 2 - equal to zero 3 - greater than zero

All addressing modes are applicable. If the literal mode is specified, the 18-bit effective operand is loaded into the specified accumulator; the leftmost bit is treated as a sign bit and is propagated to the left across the accumulator.

4.1.2 Load Half-Word (11)

The content of the half-word whose leftmost byte is specified by the effective address is inserted into the half of the A accumulator specified in the M field.

The M field can also specify that the half-word is to be loaded into the right half of accumulator A with the sign bit propagated across the accumulator.

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operation repertoire

The M field is set as follows:

01 -left half 10 - right half

11 - right half with extended sign

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the content of the entire A accumulator is compared to zero, and the condition indicator is set as follows:

1 - less than zero 2 - equal to zero 3 - greater than zero

All addressing modes are applicable. If the literal mode is specified, the rightmost 16 bits of the effective operand are inserted in the specified position of the A accumulator.

4.1.3 Load Byte (00)

The content of the byte specified by the effective address is inserted into the A accumulator in the position specified in the M field.

The unspecified bytes of the A accumulator are not affected.

The M field is set as follows:

00 - byte 1 (leftmost byte) 01 - byte 2

10 - byte 3 II-byte 4

1 - less than zero 2 - equal to zero 3 - greater than zero

All addressing modes are applicable. If the literal mode is specified, the rightmost byte of the effective operand is inserted into the specified position of the A accumulator.

4.1.4 Load Byte and Clear (01)

The content of the byte specified by the effective address is inserted into the A accumulator in the position specified in the M field.

Each bit in the remaining bytes of the A accumulator is set to zero.

The M field is set as follows:

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00 - byte 1 (leftmost byte) 01 - byte 2

10 - byte 3 II-byte 4

Revised 30 June 1970

operation repertoire

1 - less than zero 2 - equal to zero 3 - greater than zero

All addressing modes are applicable. If the literal mode is specified, the rightmost byte of the effective operand is inserted into the specified position of the A accumulator.

4.1.5 Load Selective (37)

Selected bits in the A accumulator are replaced by the corresponding bits of the word whose leftmost byte is specified by the effective address. Where a one occurs in the B accumulator, the corresponding bit in the A accumulator is set to the same state as the bit in the memory word. Otherwise the bit in the A accumulator is undisturbed. Thus, the content of B is a mask that controls the loading of A.

The M field is ignored for this operation.

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the condition indicator is set as follows:

1 - all bits are one in accumulator A 2 - all bits are zero in accumulator A

3 - neither of the above; accumulator A contains mixed zeros and ones

All addressing modes are applicable. When the literal addressing mode is specified the leftmost bit of the effective operand is propagated to the left to form a 32-bit operand.

4.1.6 Load Magnitude Accumulator (lD)

The absolute value of the word(s) specified by the effective address is loaded into the accumulator specified in the M field.

If the specified memory location contains a negative operand, the two's complement is formed before insertion into the accumulator.

The M field is set as follows:

01- accumulator A 10 - accumulator B 11 - accumulator D

If the two's complement operation is performed on the maximum 32-bit or 64-bit negative number before insertion into the accumulator, overflow occurs and the overflow indicator is set.

1 - less than zero (overflow) 2 - equal to zero

3 - greater than zero

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operation repertoire

All addressing modes are applicable. If L equals one, the leftmost bit of the. absolute value of the IS-bit effective operand is propagated to the left to form the 32-bit or 64-bit operand. If a negative literal is found, the leftmost bit of the literal is propagated to the left before the literal is negated.

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If the literal mode is specified, overflow cannot occur, since the maximum 32-bit negative number cannot be expressed as an IS-bit literal.

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4.1.7 Load Index Register (09)

The rightmost IS-bits of the word whose leftmost byte is specified by the effective address is inserted into the index register specified in the M field.

The M field is set as follows:

01 - index register 1 10 - index register 2 11 - index register 3

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the content of the specified index register is compared to zero, and the condition indicator is set as follows:

1 - leftmost bit is one

2 - index register content equal to zero

3 - index register content nonzero and leftmost bit is zero·

It should be noted that the index register content is always treated as an unsigned integer.

All addressing modes are applicable.

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4.1.8 Store Accumulator (54)

Either the content of the accumulator specified in the M field or implied zeros are stored in the word(s) whose leftmost byte is specified by the effective address.

The M field is set as follows:

00 - zeros

01 - accumulator A 10 - accumulator B 11 - accumulator D

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the content of the entire accumulator (word or double-word) is compared to zero, and the condition indicator is set as follows:

1 - less than zero 2 - equal to zero 3 - greater than zero

The direct and indirect addressing modes are applicable.

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operation repertoire

Note

If the literal and indirect modes of this instruction are both specified, the effective operand is stored in the address field of the first word found having the indirect bit equal to zero. If the literal mode is not specified, the operand address is obtained from this location as usual.

4.1.9 Store Half-Word (5E)

The content of the half of the A accumulator specified in the M field is stored in the half-word whose leftmost byte is specified by the effective address.

The M field is set as follows:

01 - left half 10 - right half

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the content of the accumulator (half-word) is compared to zero, and the condition indicator is set as follows:

1 - less than zero 2 - equal to zero 3 - greater than zero

. The direct and indirect addressing modes are applicable.

4.1.10 Store Byte (4E)

The content of the byte of the A accumulator specified in the M field is stored in the byte specified by the effective address.

The M field is set as follows:

00 - byte 1 (leftmost byte) 01- byte 2

10 -byte 3 I1-byte 4

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the content of the specified accumulator (byte) is compared to zero, and the condition indicator is set as follows:

1 - less than zero 2 - equal to zero 3 - greater than zero

The direct and indirect addressing modes are applicable.

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Revised 30 June 1970 4-5

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operation repertoire

14.1.11 Store Selective (69)

For each bit in the B register set to one, the corresponding bit in the memory word is set to the value of the corresponding bit in the A register. All other bits in the memory word are undisturbed. The leftmost byte of the memory word is specified by the effective address. Thus, the content of the B register forms a mask that controls the storage operation.

The M field is ignored for this instruction.

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the content of the specified storage location (word) is examined, and the condition indicator is set as follows:

1 - all bits are one in the memory word 2 - all bits are zero in the memory word

3 - neither of the above; the result is mixed zeros and ones The direct and indirect addressing modes are applicable.

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4.1.12 Store Magnitude (55)

The absolute value of the accumulator specified in the M field is stored in memory beginning at the word(s) whose leftmost byte is specified by the effective address.

If the content of the accumulator is a negative operand, the two's complement is formed before the storage operation is performed.

The M field is set as follows:

01- accumulator A 10 - accumulator B 11 - accumulator D

If the two's complement operation is performed on the maximum 32-bit or 64-bit negative number before insertion into memory, overflow occurs and the overflow indicator is set.

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the content of the specified accumulator is compared to zero, and the condition indicator is set as follows:

1 -less than zero (overflow) 2 - equal to zero

3 - greater than zero

The direct and indirect addressing modes are applicable.

14.1.13 Store Magnitude Half-Word (SF)

The absolute value of the half-word of the A accumulator specified in the M field is stored in memory beginning at the half-word whose leftmost byte is specified by the effective address.

If the content of the A accumulator is a negative number, the two's complement is formed before the storage operation is performed.

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operation repertoire

The M field is set as follows:

01 - left half 10 - right half

If the two's complement operation is performed on the maximum 16-bit negative number before insertion into memory, overflow occurs and the overflow indicator is set.

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the content of the specified accumulator (half-word) is compared to zero, and the condition indicator is set as follows:

1 - less than zero (overflow) 2 - equal to zero

3 - greater than zero

The direct and indirect addressing modes are applicable.

4.1.14 Store Index Register (48)

The content of the index register specified in the M field is stored in the address field of the word whose leftmost byte is specified by the effective address.

The M field is set as follows:

01 - index register 1 10 - index register 2 11 - index register 3

1 - leftmost bit is one

2 - index register content equal to zero

3 - index register content nonzero and leftmost bit is zero

It should be noted that the index register content is always treated as an unsigned integer.

All addressing modes are applicable.

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4.1.15 Exchange Storage With Accumulator Register (40)

The content of the accumulator register specified in the M field is exchanged with the content of the word specified by the effective address.

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operation repertoire

The M field is set as follows:

01 - accumulator A 10 - accumulator B 11 - accumulator D

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the content of the specified accumulator is compared to zero after the exchange and the condition indicator is set as follows:

1 - less than zero 2 - equal to zero 3 - greater than zero

The direct and indirect addressing modes are applicable.

14.1.16 Exchange Storage With Accumulator Register and Negate (41)

The content of the accumulator register specified in the M field is exchanged with the content of the word specified by the effective address. The two's complement of the accumulator content is formed during the exchange operation.

The M field is set as follows:

01 - accumulator A 10 - accumulator B 11 - accumulator D

If the maximum 32-bit or 64-bit negative number is negated, overflow occurs and the overflow indicator is set.

1 - less than zero (overflow) 2 - equal to zero

2 - greater than zero

The direct and indirect addressing modes are applicable.

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4.1.17 Exchange Storage With Index Register (43)

The content of the index register specified in the M field is exchanged with bits 14 through 31 of the word specified by the effective address. The remaining bits of the memory word are undisturbed.

The M field is set as follows:

4-8

01 - index register 1 10 - index register 2 11 - index register 3

Revised 30 June 1970

operation repertoire

1 - leftmost bit is one

2 - index register content equal to zero

3 - index register content nonzero and leftmost bit is zero The direct and indirect addressing modes are applicable.

4.1.18 Exchange Storage With Index and Negate (53)

The content of the index register specified in the M field is exchanged with bits 14 through 31 of the word specified by the effective address. The remaining bits of the memory word are undisturbed. The two's complement of the memory word is formed during the exchange operation.

The M field is set as follows:

01 - index register 1 10 - index register 2 11 - index register 3

If the maximum 18-bit negative operand is negated, overflow occurs and the overflow indicator is set. It should be noted that the final index register content is treated as an unsigned integer.

1 - leftmost bit is one

2 - index register content equal to zero

3 - index register content nonzero, and leftmost bit is zero The direct and indirect addressing modes are applicable.

4.1.19 Transfer Register to Register (56)

This single operation code is modified by the M field to specify four individual operations. The meanings of the bits in the M field are as follows:

Most Significant Bit of M

o

Least Significant Bit of M

o

Meaning

No complement Two's complement Meaning

The effective address specifies two registers (R1 and R2) that are involved in the operation. Any pair of the following registers may be specified: A, B, Xl, X2 or X3. The D register may only be specified if R1 = R2.

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operation repertoire

The format of the word which specifies these registers is as follows:

I . .

^SPARE ^R1

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^{R i J}

~ I I I ... LLJ ...

0 13 14 15 16 23 24 31

Where A

=

1₁₆ and Xl

=

81 ₁₆ B

=

2₁₆ X2

=

82₁₆ D

=

3₁₆ X3

=

83 ¹⁶

If an index register is transferred to A or B, the leftmost 14 bits of A or B are undisturbed. If an index register is a destination register for the contents of A or B, only the rightmost 18 bits are transferred.

If two's complement is specified, R2 contains the two's complement of the content of R1 after the operation.

If the two's complement option is- taken when A or B is R1 and R1 is the maximum 32-bit negative number, overflow occurs. If the two's complement option is taken when Xl, X2, or X3 is R1 and R1 is the maximum 18-bit negative number, overflow occurs. The overflow indicator is set if overflow occurs.

The following is a list and description of the combinations that the M field can select.

00 - register to register transfer 01 - exchange registers

10 - register to register transfer and negate 11 - exchange registers and negate

Transfer register to register: The registers involved are R1, the source register, and R2 the destination register. The content of R1 is transferred to R2. The content of R1 is undisturbed.

Transfer register to register and negate: This instruction performs the same function as the transfer register to register instruction with an additional feature. R2 contains the two's complement of the content of R1 after the transfer operation is performed. The content of R1 is undisturbed.

Exchange registers: The contents of the specified registers (R1 and R2) are exchanged.

Exchange registers and negate: This instruction performs the same function as the exchange registers instruction with an additional feature. R2 contains the two's complement of the content of R1 after the exchange operation is performed.

The C field contains either a zero or one. If C equals zero, no condition indicator is set. If C equals one, the content of the destination register (R2) is compared to zero, and the condition indicator is set according to the specified destination register.

Accumulator:

1 - less than zero 2 - equal to zero 3 - greater than zero Index register:

4-10

1 - leftmost bit is one 2 - equal to zero

3 - nonzero; leftmost bit is zero

Revised 30 June 1970

operation repertoire

Note that index registers are always considered unsigned.

The effective address provides the register pair designation for this instruction regardless of the state of the L field. The register pair designation can be indirectly specified and modified by indexing.

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The exchange of a register with itself without negation is illegal and the register content is unpredictable for such an exchange.

4.2 SHIFT INSTRUCTIONS

Im Dokument instruction book (Seite 31-41)