4.3 Mixer
4.3.5 Mixer Core
Core Transistors’ Sizing
Due to AC coupling of mixer core its sizing and biasing can be decoupled from the TRC.
Therefore the core was optimized stand alone with 50 Ω input termination. A λ/4 line and a series 2 pF were used as ground DC return path and the AC coupling, respectively. The base current was supplied through 1 kΩ resistors in order not to load the bases of the core. Since these resistors are in shunt, their contribution to overall noise figure is negligible.
Mixer
IF+
Q1 LO+
IF-Q2 Vcc
LO-RF Q3
(a) Current Boosting – for each Transconductance
IF+
Q1 Vcc
LO+ Q2
LO-RF+ Q5
Q3
IF-Q4
Vcc
RF-Q6
LO+
Vcc1
(b) Current Boosting – at Virtual Ground
IF+
Q1 Vcc
LO+ Q2
LO-RF+ Q5
Q3
IF-Q4
Vcc
RF-Q6
LO+
Vcc
(c) Capacitive Coupling
IF+
Q1 Vcc
LO+ Q2
LO-RF+ Q5
Q3
IF-Q4
Vcc
RF-Q6
LO+
Vcc
(d) Transformer Coupling
Figure 4.63: Various Transconductance-to-Core Interfaces - cont.
Core transistor sizing is analyzed in bottom-to-top fashion. First, various noise contributors for each mixer core transistor are shown in table 4.6 over various core size and bias values. The contributors are displayed in dynamic range of 30 dB. The noise contributions are referenced to the input since this allows the comparison between various cases (by taking out the dependence on conversion gain). Several observations can be made:
“Sanity check”: the various inter-transistor noise contributors are independent and in-deed add up to the total noise value:
1.252 u 0.812+ 0.552+ 0.492+ 0.482+ 0.312+ 0.212 (4.22)
1.252 u 1.569 (4.23)
(the check was performed for the 8-cell sizing, 14.4 mA overall core bias current).
The current density for all sizings was retained the same. In general, the different con-tributors for all sizings are quite balanced, which is a sign of an optimal design.
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Design of Circuits
The transistors have lowest noise contributions for 4-cell sizing, while 8-cell and 2-cell core are comparable noise-wise.
All the contributors are similar apart from the 8-cell, 14.4 mA case, where due to tran-sistor size and higher bias the collector shot contribution is higher.
The smallest devices were not considered for the core since process spread could contribute to imbalance and eventually, to performance degradation.
Table 4.6: Core Transistors’ Input-referenced Major Noise Contributions’ Breakdown
Cells
Bias Each itzf flicker rbi rbx re ibe
Transistor (Collector, ibe (Thermal, (Thermal, (Thermal, (Shot
Total Shot) Base Base Emitter Base)
Noise Intrinsic Extrinsic Resistor) Resistor) Resistor)
[mA] h
√nV Hz
i h
√nV Hz
i h
√nV Hz
i h
√nV Hz
i h
√nV Hz
i h
√nV Hz
i h
√nV Hz
i
8
14.4 1.25 0.81 0.55 0.49 0.48 0.31 0.21
10.5 1.10 0.76 0.47 0.41 0.41 0.26 0.18
6.2 0.96 0.7 0.36 0.33 0.32 0.22 0.15
4
7.1 1.03 0.64 0.56 0.37 0.38 0.25 0.19
5.2 0.98 0.62 0.47 0.36 0.36 0.23 0.16
3.1 0.87 0.60 0.33 0.33 0.34 0.22 0.12
2
3.57 1.20 0.64 0.68 0.45 0.47 0.31 0.20
2.62 1.15 0.65 0.58 0.46 0.47 0.31 0.17
1.57 1.02 0.65 0.42 0.45 0.44 0.30 0.13
Secondly, it was crucial to see how the core transistors’ noise compare with the other noise sources, such as input port and load noise (table 4.7). Several observations can be made here as well:
“Sanity check”: the core noise contributors are independent and indeed add up to the total noise value:
2.72 u 4·1.252+ 0.812+ 0.592 (4.24)
2.72 u 7.254 (4.25)
(the check was performed for the 8-cell sizing, 14.4 mA overall core bias current).
The core consists of 4 independent transistors, so the overall transistors noise contribution is larger than the ports’ noise contributions.
Due to increase of gain with the transistor sizing the load noise contribution related to the input goes down.
Mixer
The change of input port noise contribution indicates change of mixer input impedance with the transistor size and bias sweep. This is due to lack of additional matching circuit between the core and the TRC. This change is not significant, though.
Table 4.7: Core Input-referenced Major Noise Contributions’ Breakdown
Cells
Bias Gvoltage Total Each Input RLOAD Noise Transistor Port
Total Noise
[mA] [ ] h
√nV Hz
i h
√nV Hz
i h
√nV Hz
i h√nV Hz
i
8
14.4 2.12 2.7 1.25 0.81 0.59
10.5 2.02 2.42 1.11 0.82 0.62
6.2 1.86 2.19 0.96 0.81 0.67
4
7.1 1.74 2.43 1.03 0.88 0.72
5.2 1.63 2.34 0.98 0.88 0.77
3.1 1.48 2.22 0.87 0.84 0.84
2
3.57 1.32 2.73 1.20 0.89 0.95
2.62 1.21 2.70 1.15 0.88 1.03
1.57 1.08 2.61 1.02 0.81 1.16
Thirdly, mixer core linearity and gain performance is shown alongside core noise performance as function of core sizing and bias (table 4.8). Unlike the noise figure, the gain and linearity monotonically increase with bias and core up-sizing. The NF of the 8-cell core at the highest bias current is 2 dB worse compared to the minimum NF case, however the 8-cell core has 7.5 dB higher linearity, and 3 dB higher power gain. The benefit of having much higher linearity out-weighted the noise optimization. Therefore the core was realized with 8-cell devices to be operated at higher bias. Mixer NF is improved by having the transconductance stage in front of the core. An optimization of DC return path (chosen asλ/4) and the AC-coupling capacitor (2 pF) could have yielded better performance, for example a shorter microstrip line would act like an inductor and resonate out some of the switches’ capacitance. Due to limited time, this optimization did not take place.
LO Interface
Switching the mixer with sufficient LO power is crucial for proper mixing operation with regard to all performance criteria [65], [83]. Two main different approaches to mixer LO port interfacing were identified:
Active, buffered interface [34], [81] – common collector (CC) stages preceding the core bases. A typical CC stage is presented on Fig. 4.64 (the current sources can be replaced by resistors or resonators). The CC stage has:
91
Design of Circuits
– high input impedance so it could properly load a differential amplifier, which could be used either as active balun or an amplifying stage;
– low output impedance, being effectively a LO voltage source driving the core bases (an HBT ideally is a voltage controlled current source).
Vcc
IN
OUT Vcc Q1
Q2 (from LO
BALUN)
(to mixer LO interface)
Figure 4.64: LO Common-Collector Buffer
LO matching [65], [51], [57], [54]. The previous approach originates in analog design, where parasitics are less explicit. At higher millimeter-wave frequencies parasitic capac-itances come into play. In case of CC this would mean shunting (reduction) of input impedance and an additional imaginary output impedance part, limiting the voltage swing. The core transistors also have parasitics, further lowering the voltage swing by introducing an additional complex part to its input impedance. This solution comes to solve it with traditional RF means of resonating out all the complex impedance parts.
The fundamental difference to the previous case is that here LO voltage is divided be-Table 4.8: Simulated Core Performance vs. Size and Bias Sweep
Cells Bias NFSSB iP1dB Power Gain
[mA] [dB] [dBm] [dB]
8
14.4 13.5 1 3.5
10.8 12.4 -1.5 3.1
7.5 11.7 -3.6 2.4
4
7.15 11.87 -3.3 1.8
5.38 11.5 -4.5 1.25
3.75 11.4 -6.5 0.4
2
3.57 12.8 -6 -0.6
2.7 12.75 -7.5 -1.3
1.9 13 -9.5 -2.3
1
1.8 15.1 -9.3 -3.6
1.35 15.4 -11.5 -4.4
0.96 16 -12 -5.5
1 6.14a 17.6 -2 -1.3
aHere the 4 core transistors are biased close to the maximal allowable current 1.8 mA per cell.
Mixer
tween the LO source and the core LO input while in the previous, CC case ideally all the available LO voltage is applied to the core. (As explained, in the high-frequency case there is voltage drop due to Op-Amp, buffer and core transistors’ parasitics).
Since this mixer is a basic building block and the end goal is the 2-channel receiver, none of these approaches were used. LO CMRR is being taken care of by a balun, that feeds directly the core bases. The balun has 50 Ohm interfaces and no additional impedance matching for either maximal power transfer or maximal voltage on the core transistors’ bases took place.
The mixer was characterized with LO of circa 4 dBm and no significant performance change was observed in the vicinity of this LO power so it was concluded that LO-wise the switches are saturated enough. Deploying matching approach the needed LO power could have been reduced by circa 1.5...2 dB but LO power optimization was not the objective of this design.