Numerous mnemonic constructs are used to represent things that do not fit easily into the rest of the notation described above or whose details are more implementation-dependent than defined.
xor(x1, ..., xn) Produces the bitwise exclusive or of the passed arguments.
zero_ext(x,len) Extends x on the left, for the field of size len, with zeros to form a 32-bit quantity.
zero_ext_64(x,len) Identical to zero_ext(x,len) except that it extends the value to 64 bits:
return(cat(0{0..31},zero_ext(x,len)))
Function Description
absolute_address(space,offset) Returns the absolute address corresponding to the passed virtual address.
alloc_DTLB(space,offset,entry) Allocates a slot in the data TLB based on the space and offset arguments. The position of the slot is returned through the pointer called entry.
alloc_ITLB(space,offset,entry) Same as alloc_DTLB, except that a new slot is allocated in the instruction TLB.
broadcast_purge_DTLB(space,offset) In a multiprocessor system, the other processors are made to search their data TLBs for a translation matching the specified virtual address.
If found, they invalidate, remove, or alter the matching entries.
broadcast_purge_ITLB(space,offset) In a multiprocessor system, the other processors are made to search their instruction TLBs for a translation matching the specified virtual address.
If found, they invalidate, remove, or alter the matching entries.
coherence_index(space,offset) Returns the coherence index corresponding to the passed effective address. See “Cache Coherence with I/O” on page 3-17.
coherent_system Boolean; the value is 1 if the system is fully
coherent; the value is 0 if the system is partially or completely non-coherent.
coprocessor_condition(id,opcode,n) A coprocessor specific condition is returned based on the arguments and the current state of the coprocessor.
coprocessor_op(id,opcode,n,priv) A coprocessor specific operation is performed based on the arguments and the current state of the coprocessor.
Function Description
flush_data_cache(space,offset) If the cache line containing the effective address is present, it is invalidated. If the line is dirty, it is written back to main memory.
flush_data_cache_entry(space,offset) Zero or more cache lines specified by an implementation-dependent function of the address are invalidated. If any of these lines are dirty, they are written back to main memory.
flush_instruction_cache(space,offset) If the cache line containing the effective address is present, it is invalidated. If the line is dirty it is written back to main memory.
flush_instruction_cache_entry(space,offset) Zero or more cache lines specified by an implementation-dependent function of the address are invalidated. If any of these lines are dirty, they are written back to main memory.
level_0 Boolean; the value is 1 if the processor
architecture is Level 0.
measurement_enabled Boolean; when the value is 1, the performance monitor coprocessor is enabled to make measurements; when the value is 0, the measurements are disabled. This condition is independent of the state of CCR bit 2.
phys_mem_load(addr,low,high,hint) Returns the data in physical memory (consisting of memory and the cache) starting at the low’th bit beyond the beginning of the byte at address, addr, and ending at the high’th bit beyond the beginning of the byte at address, addr. If the PSW E-bit is 1, the data bytes are swapped before they are returned. The cache control hint, hint, is a recommendation to the processor on how to resolve cache coherence. See “Cache Control” on page 5-17. This function is used for absolute accesses to memory.
phys_mem_store(addr,low,high,hint,data) Stores the data in physical memory (consisting of memory and the cache) starting at the low’th bit beyond the beginning of the byte at address, addr, and ending at the high’th bit beyond the beginning of the byte at address, addr. If the PSW E-bit is 1, the data bytes are swapped before they are stored.
The cache control hint, hint, is a recommendation to the processor on how to resolve cache coherence. See “Cache Control” on page 5-17.
This function is used for absolute accesses to memory.
Function Description
purge_DTLB(entry) The specified TLB entry is invalidated, removed, or altered.
purge_DTLB_entry(entries) The E-bit(s) of the zero or more data TLB entries specified are set to 0. All other fields of these TLB entries are undefined.
purge_ITLB(entry) The specified TLB entry is invalidated, removed, or altered.
purge_ITLB_entry(entries) The E-bit(s) of the zero or more instruction TLB entries specified are set to 0. All other fields of these TLB entries are undefined.
purge_or_flush_data_cache(space,offset) If the cache line specified by the effective address is present, it is invalidated. If the line is dirty, it may optionally be written back to memory.
read_access_allowed(space,offset,x) In non-Level 0 systems, returns 1 if read access is allowed to the effective address at the privilege level given by the two rightmost bits of x. Returns 0 otherwise. Always returns 1 in Level 0 systems.
search_DTLB(space,offset,entry) Searches the data TLB for an entry (valid or invalid) whose virtual address matches the virtual address passed to it, and returns true if it finds one.
As a side effect, if such a translation is found, the variable entry is set to point to the TLB slot containing this translation.
search_ITLB(space,offset,entry) Same as search_DTLB, except that the instruction TLB is searched.
select_data_cache_entries(space,offset) An implementation-dependent function which returns a list of zero or more entries.
select_instruction_cache_entries(space,offset) An implementation-dependent function which returns a list of zero or more entries.
select_DTLB_entries(space, offset) An implementation-dependent function which returns a list of zero or more entries.
select_ITLB_entries(space, offset) An implementation-dependent function which returns a list of zero or more entries.
sfu_condition0(opcode,priv) sfu_condition1(opcode,priv) sfu_condition2(opcode,priv,r) sfu_condition3(opcode,priv,r1,r2)
An SFU specific condition is returned based on the SFU instruction format, the arguments, and the current state of the special function unit.
sfu_operation0(opcode,priv) sfu_operation1(opcode,priv) sfu_operation2(opcode,priv,r) sfu_operation3(opcode,priv,r1,r2)
An SFU specific operation is performed based on SFU instruction format, the arguments, and the current state of the special function unit.
Function Description
space_select(s_field,base) Returns the space ID selected by the s-field of the instruction and the base register value as follows:
space_select(s_field,base)
virt_mem_load(addr,low,high,hint) Returns the data in virtual memory (consisting of memory and the cache) starting at the low’th bit beyond the beginning of the byte at address, addr, and ending at the high’th bit beyond the beginning of the byte at address, addr. If the PSW E-bit is 1, the data bytes are swapped before they are returned. The cache control hint, hint, is a recommendation to the processor on how to resolve cache coherence. See “Cache Control” on page 5-17. This function is used for virtual accesses to memory.
virt_mem_store(addr,low,high,hint,data) Stores the data in virtual memory (consisting of memory and the cache) starting at the low’th bit beyond the beginning of the byte at address, addr, and ending at the high’th bit beyond the beginning of the byte at address, addr. If the PSW E-bit is 1, the data bytes are swapped before they are stored.
The cache control hint, hint, is a recommendation to the processor on how to resolve cache coherence. See “Cache Control” on page 5-17.
This function is used for virtual accesses to memory.
write_access_allowed(space,offset,x) In non-Level 0 systems, returns 1 if write access is allowed to the effective address at the privilege level given by the two rightmost bits of x. Returns 0 otherwise. Always returns 1 in Level 0 systems.
Function Description
Instruction Descriptions
Figure 5-1 illustrates the information presented in each of the instruction descriptions. The information presented in this figure is for illustrative purposes only and does not represent a valid instruction.
Figure 5-1. Instruction Description Example
DO OPERATION DO
Format: DO,cond r1,r2,t
Purpose: To perform a 32-bit, bitwise DO operation.
Description: GR r1 and GR r2 are DOed and the result is placed in GR t. The following instruction is nullified if the values DOed satisfy the specified condition, cond. The condition is encoded in the c and f fields of the instruction.
Conditions: The condition is any of the logical conditions (Table 5-5 on page 5-6). When a condition completer is not specified, then the
"never" condition is used. The boolean variable "cond_satisfied" in the operation section is set to 1 when the values DOed satisfy the specified condition.
Operation: GR[t] ← GR[r1] DO GR[r2];
if (cond_satisfied) PSW[N]← 1;
Exceptions: None Restrictions: None
Notes: The DOIT pseudo-operation allows for the transformation of data from one register to another by generating the instruction DO r,0,t.
The DONT pseudo-operation generates the instruction DO 0,0,0.
Level 0: No restrictions.
5-98 Instruction Set PA-RISC 1.1 Architecture
5Instruction Set