. . LDW
RFI ; dispatch process
Because no TLB miss fault can occur, the interruption handler need not incur the overhead of disabling code translation just prior to process dispatch. Note that the LDW instructions in this sequence must use absolute addresses. (Use absolute loads, or do these with the PSW D-bit equal to 0.)
Data Cache Move-In
Data lines are brought into the cache only as a result of references, and only if the page containing the reference is cacheable. Except where noted, a data reference may move in all of the lines on the cacheable page containing the reference. The following actions constitute a data reference, and may cause move-in to the data cache:
• Execution of a load, store, or semaphore instruction
• Interruption of a load, store, or semaphore instruction by any interruption except the ones listed below:
Intr. No. Interruption
6 instruction TLB miss fault
7 instruction memory protection trap 8 illegal instruction trap
10 privileged operation trap 15 data TLB miss fault
18 data memory protection/unaligned data reference trap 19 data memory break trap
20 TLB dirty bit trap 21 page reference trap
26 data memory access rights trap 27 data memory protection ID trap 28 unaligned data reference trap
NOTE
Because protection is checked (interruptions 10, 18, 26, and 27), the reference cannot bring in any data which could not have been accessed. This does not apply, however, to absolute accesses.
• A load or store instruction which is left at the front of the interruption queues because of a prior instruction which took a group 4 interruption, provided that the load or store would not have taken any of the above interruptions (6, 7, 8, 10, 15, 18, 19, 20, 21, 26, 27, 28).
Data items which would have been referenced by a nullified load, store, or semaphore instruction are not moved in.
The instructionsLDWAX,LDWAS, andSTWAS are exceptions to the general rule that a data reference may cause all of the lines in the page containing the reference to be moved in. These instructions can cause only the referenced line to be moved into the data cache.
In addition to the above rules, the following properties determine if the cache line associated with a memory reference may be moved into the data cache or a combined data and instruction cache:
• Whether the memory reference is virtual or absolute.
• Whether or not the optional TLB U (Uncacheable) bit is implemented.
• The state of the U-bit, if implemented.
• Whether the reference is made to a page in the memory or the I/O address space.
Table 3-2 specifies the rules under which the above properties determine if a memory reference may be moved into the data cache.
Instruction Cache Move-In
Instructions are brought into the instruction cache, or combined data and instruction cache, only as a result of references. Except where noted, an instruction reference may move in all of the lines on the page containing the reference, as well as all of the lines on the next sequential page, provided access and
TLB U-bit Table 3-2. Data Cache Move-In Rules
protection check requirements are met for each page. (If the PSW C-bit is 0, then the next sequential page is the next sequential physical page. Otherwise, if the PSW C-bit is 1, then it is the next sequential virtual page.) The following actions constitute an instruction reference, and may cause move-in to the instruction cache:
• Execution of an instruction
• Execution of a nullified instruction which would not have taken any of the following interruptions had it not been nullified. This action can cause only those lines on the page containing the instruction to be moved in
NOTE
Because protection is checked (interruption 7) the reference cannot bring in any instructions which could not be executed. This does not apply, however, to absolute accesses.
• Execution of a branch can cause all of the lines on the page containing the target of the branch to be moved in.
• Execution of a branch to a target instruction which is the last instruction on a page, followed by an instruction which traps (in the branch delay slot), can cause all of the lines on the page containing the target instruction, as well as all of the lines on the next sequential page to be moved in.
• Interruption of an instruction by any interruption except for the ones listed below:
• A branch instruction which takes a group 4 interruption can cause all of the lines on the page containing the instruction which would have been branched to, to be moved in.
Instructions which would have been branched to by nullified or untaken branches are not moved in.
If lines on the next sequential page are to be moved in, that page must meet the normal access and protection check requirements.
PROGRAMMING NOTE
If a data page immediately follows an instruction page, it is possible that the entire data page may have been moved into the instruction cache because of these move-in rules. Software must be aware of this fact and flush both the instruction and the data caches in order to remove the data page from the cache.
Intr. No. Interruption
6 instruction TLB miss fault
7 instruction memory protection trap
Intr. No. Interruption
6 instruction TLB miss fault
7 instruction memory protection trap
To insure that lines from a particular data page are not moved into the instruction cache, software must not make absolute instruction references to the immediately preceding physical page, and must prevent virtual instruction references to the data page. This latter can be accomplished by not assigning execute access rights to the data page. If, however, the data page is assigned execute access rights, and virtual instruction references are prevented by some other means, then software must also prevent virtual instruction references to the immediately preceding page.
In addition to the above rules, the following properties determine if the cache line associated with a instruction reference may be moved into the instruction cache or a combined data and instruction cache:
• If the reference is made to a page in the memory address space, the referenced line may be moved into the cache.
• If the reference is made to a page in the I/O address space, the referenced line must not be moved into the cache.
• If there is a combined instruction and data TLB, then an instruction fetch from a page with its U-bit 1 is undefined.
Flushing
A flush cache, purge cache, or purge TLB instruction to a page stops (disables) any subsequent move-in operations to that page until another reference to that page is made. In a multiprocessor system, these instructions stop any subsequent move-in operations to that page on all processors until another reference to that page is made.
Once a reference has been made, and a line could have been brought into a cache, the only way software can insure that the line has been removed from the cache is to flush or purge it and execute aSYNC instruction, or to flush the entire cache with flush-entry instructions and execute aSYNC instruction.
Once a line is referenced, even if it is subsequently forced out of the cache by other references, the cache system can move it in again without another reference, until the line is flushed.