The 32-bit arithmetic/logical operations generate the set of conditions as shown in Table 5-1. No overflow conditions result from logical operations. In the table, c is the machine language encoding indicating the condition. The conditions are computed based on the 32-bit result of the arithmetic operation, the (leftmost) carry bit of the result, and the overflow indication. The terms signed overflow and unsigned overflow are defined for the arithmetic instructions in Table 5-2.
When implementing the DIVIDE STEP and SHIFT AND ADD instructions, the overflow condition XORed into conditions 2 and 3 may optionally include the overflow that is generated during the pre-shift operation. The only overflow that must be included is the one actually generated by the arithmetic
Table 5-1. Arithmetic/Logical Operation Conditions
c Description
0 never; nothing 1 all bits are 0
2 (leftmost bit is 1) xor signed overflow
3 all bits are 0 or (leftmost bit is 1 xor signed overflow)
adds subtracts/compares
4 no unsigned overflow unsigned overflow
5 all bits are 0 or no unsigned overflow all bits are 0 or unsigned overflow 6 signed overflow
7 rightmost bit is 1
Table 5-2. Overflow Results
Instructions Unsigned Overflow Signed Overflow
Adds The result of an unsigned addition is greater than (carry == 1).
The result of signed addition is not representable in 32-bit two’s complement notation (both source operands have the same sign and the sign of the 32-bit result is different)
Subtracts and Compares
The result of an unsigned subtraction is less than 0 (i.e., b is greater than a in the
operation c = a - b; borrow ==
0).
The result of signed subtraction is not representable in 32-bit two’s complement notation (both the source operands have different signs and the sign of the 32-bit result differs from the sign of the first operand; i.e., a has a different sign than b and c in the operation c = a -b).
Divide Step and Shift and Adds
One or more of the bits shifted out is 1, or the result of the operation is not in the range 0
through .
One or more of the bits shifted out differs from the leftmost bit following the shift, or the result of the operation is not representable in 32-bit two’s complement notation.
232–1
232–1
operation.
If a signed overflow occurs during the shift operation of aDIVIDE STEP orSHIFT AND ADD instruction, conditions 2 and 3 are not meaningful; therefore, the result of a condition 2 or condition 3 test is not predictable.
PROGRAMMING NOTE
The figure below shows signed number addition and indicates the signed overflow condition when both operands are small positive numbers, large positive numbers, large negative numbers, or small negative numbers.
Signed overflow can occur only when adding numbers with the same sign. Addition of numbers with unlike signs will always result with a "no overflow" condition.
The interpretation of the arithmetic/logical conditions varies according to the operation performed. The interpretation for comparisons and subtracts is shown in Table 5-3. In this table, cond is in assembly language format and c and f are in machine language format. opd1 denotes operand 1 (an immediate value or a register’s contents) in the assembly language instruction format and opd2 denotes operand 2 (a register’s contents). The condition, <<, "opd1 is less than opd2 (unsigned)" is equivalent to unsigned overflow in Table 5-1.
0 overflowno 1 overflow 0 overflow 1 overflowno
The interpretation for adds is shown in Table 5-4. Cond is in assembly language format and c and f are in machine language format.
The interpretation of the condition completers for the SHIFT AND ADD instructions is similar to the ADD instructions (Table 5-4). If no overflow occurs, opd1 is the shifted value. For example, the completer "=" implies that the shifted opd1 equals the negative of opd2. If overflow occurs, the interpretations in Table 5-4 do not apply. Table 5-1 and the definition of overflow in Table 5-2 can be
Table 5-3. Compare/Subtract Instruction Conditions
cond Description c f
never 0 0
= opd1 is equal to opd2 1 0
< opd1 is less than opd2 (signed) 2 0
<= opd1 is less than or equal to opd2 (signed) 3 0
<< opd1 is less than opd2 (unsigned) 4 0
<<= opd1 is less than or equal to opd2 (unsigned) 5 0
SV opd1 minus opd2 overflows (signed) 6 0
OD opd1 minus opd2 is odd 7 0
TR always 0 1
<> opd1 is not equal to opd2 1 1
>= opd1 is greater than or equal to opd2 (signed) 2 1
> opd1 is greater than opd2 (signed) 3 1
>>= opd1 is greater than or equal to opd2 (unsigned) 4 1
>> opd1 is greater than opd2 (unsigned) 5 1
NSV opd1 minus opd2 does not overflow (signed) 6 1
EV opd1 minus opd2 is even 7 1
Table 5-4. Add Instruction Conditions
cond Description c f
never 0 0
= opd1 is equal to negative of opd2 1 0
< opd1 is less than negative of opd2 (signed) 2 0
<= opd1 is less than or equal to negative of opd2 (signed) 3 0
NUV opd1 plus opd2 does not overflow (unsigned) 4 0
ZNV opd1 plus opd2 is zero or no overflow (unsigned) 5 0
SV opd1 plus opd2 overflows (signed) 6 0
OD opd1 plus opd2 is odd 7 0
TR always 0 1
<> opd1 is not equal to negative of opd2 1 1
>= opd1 is greater than or equal to negative of opd2 (signed) 2 1
> opd1 is greater than negative of opd2 (signed) 3 1
UV opd1 plus opd2 overflows (unsigned) 4 1
VNZ opd1 plus opd2 is nonzero and overflows (unsigned) 5 1
NSV opd1 plus opd2 does not overflow (signed) 6 1
EV opd1 plus opd2 is even 7 1
used to determine if the condition is satisfied.
The interpretation of the condition completers for the DIVIDE STEP instruction are similar to the subtract or add conditions, depending on the state of the PSW V-bit. If no overflow occurs, then opd1 is the shifted value. If overflow occurs, the interpretations in Tables 5-3 and 5-4 do not apply. Again, Tables 5-1 and 5-2 can be used to determine if the condition is satisfied.
For logical operations, the conditions are computed based only on the result. The interpretation of the arithmetic/logical conditions for logical instructions is shown in Table 5-5. In this table, cond is in assembly language format and c and f are in machine language format. The unlisted values of the condition field are undefined for the logical operations.