implemented. This on the other hand would introduce a different temperature induced delay behavior, as this depends on the active delay tabs, which are then different for the two delay circuits.
3. Finally, the transfer function of the two phase comparators (see Figure 4.6) is neither fully linear (around 0 degrees and +-180 degrees) nor is it free of ambiguities (-180 degrees to 0 degrees is the same as 0 degrees to +180 degrees). All these cases influence the controller and have to be implemented. For the measurements described here, a simplified implementation have been used and care was taken, that the conditions were valid.
5.4 Measurement results
The main goal of this measurement has been to evaluate the performance of the drift compen-sation scheme (i.e. if the drift compencompen-sation scheme and the chosen components are able to reduce phase drifts induced by temperature changes on the fiber connection significantly below the desired 10ps RMS for the recovered reference clock transmitted over the fiber).
The measurement detected the phase error between the reference clock of the transmitter and the recovered clock, when (1) the drift compensation is disabled and (2) when the drift com-pensation is enabled. Both measurements have been successively performed over a time of 12 hours. The temperature on the fiber connection for both measurements have been in between 17 centigrades and 24 centigrades. The measured maximum phase error in case of no drift compensation has been 63ps and with the drift compensation enabled, only 3.3ps. In these measurements, influence of asymmetric behavior and equal length of the used fibers, asymmet-ric behavior of the delay components, influence of ADC and DAC conversion and PID control parameter choice has not been analyzed, included or optimized. However, the measured perfor-mance showed, that even in this state the system is able to sufficiently reduce the introduced phase drift.
Chapter 6
MicroTCA hardware platform
Timing related signals play a key role in data acquisition and control systems. Most of the hardware is available or designed as modules used inside numerous enclosures (crates). There-fore the used crate standard should support distribution and configuration of timing related signals in an optimal way (e.g. low-noise, low-jitter, high-bandwidth, flexibility, etc.). This chapter provides an introduction to the used standard for the European XFEL and describes some details about timing related aspects. Further information about how the timing system will provide the relevant signals or interface to the other components will be discussed in later chapters.
6.1 Time of transition
Modular crate systems are commonly used at large scale research experiments like particle accelerators. Those systems consist of a mechanical frame called crate, which allows a number of electronic modules to be inserted. Usual modules are computing units, digitizers (analog-to-digital converters, ADCs), (analog-to-digital-to-analog converters (DACs), (analog-to-digital input and output units and numerous specialized types of modules. The communication and data transfer between modules (classically between the computing unit and the other available modules) are medi-ated via a backplane, which is connected with all boards via sockets with multiple pins (see Figure 6.1).
Figure 6.1: Example of a crate (in this case in the VME standard) consisting of a metal frame, a backplane with connectors to connect the inserted modules and a power supply with fan unit (source: http://www.caen.it)
In the past, two of the most commonly used crate standards were CAMAC (Com-puter Automated Measurement And Control) and VME (Verso Module Eurocard). Newer and smaller standards like cPCI (compact Peripheral Component Interconnect) and PXI from Na-tional Instruments followed. But these standards share a common principle: communication and data transfer between modules are accomplished via parallel buses and dedicated interrupt lines. As parallel buses where always known to be the communication with highest bandwidth, this was the best solution to implement. However, a common parallel bus has also disad-vantages, which nowadays outweigh the advantages and some of them should be mentioned briefly:
• On a common bus only one connected module can access the bus at a time. That implies, that transfer of data has to be time multiplexed. If there is more than one master on a bus, only one can take control of the bus at a time, even if a second master would like to transfer data between completely different modules.
• Buses in the mentioned standards are implemented as single ended signals with relatively high voltage levels (around three to five Volts). If multiple lines of the bus are switched in parallel, electromagnetic effects could influence sensitive analog components on modules like ADCs.
• The transmission bandwidth on the bus is limited due to stubs for each connected module and bus arbitration schemes. Especially compared to current high-speed serial serdes (serialize / deserialize) technologies, which allow more than 10 GHz of switching speed on a single differential line.
An important part of the implemented solution in new generations of crates is therefore to switch from buses to multiple serial point-to-point connections. As they are point-to-point, the termination is at the endpoints of a differential communication channel and therefore reflections are minimized. No stubs exist and no arbitration of the channel is required. Therefore high communication speed can be achieved. Bundling of such channels allows a further increase of bandwidth. Dedicated point-to-point connections allow communication between different modules at the same time. Configurable switches allow changing of communication partners.