In order to measure the full performance of the drift compensation under realistic conditions, a setup has been prepared as shown in Figure 8.5 consists of two Timing modules, where one acts as the Transmitter and the other as the Receiver module. Both are connected via two optical fibers (one for transmitting from the transmitter to the receiver and one to return the signal from the receiver to the transmitter) with a length of 4km. The fibers are within one single cable on a spool. This connection represents slightly more than the largest assumed distance between transmitter and receiver for the European XFEL. Additionally the spool is placed in a way, that different temperatures can be applied to the fiber in order to simulate temperature induced drifts. In this case the spool either placed outside of the building to use the day and night cycles or inside an oven (climate chamber). Additionally, a reference 1.3GHz clock is provided by a Rohde & Schwarz SMB100A clock generator and applied to the transmitter module through the SMA input.
In order to measure the phase relation between transmitter and receiver, both modules generate a 108MHz clock with their internal clock distribution and divider section, which is making use
Figure 8.5: Block diagram of the drift measurement setup. Two Timing modules are placed in a MicroTCA crate. One is used as (Master) Transmitter and the other as Receiver. The Transmitter received a reference 1.3GHz clock from a clock generator (Rohde & Schwarz SMB100A). The Transmitter and Receiver are connected via two optical fibers within one cable on a cable spool. The length of each fiber is 4km. The spool has been placed outside of the building or into an oven in order to experience a temperature change.
A temperature sensor is placed at the spool (not shown). Both modules generate an 108MHz output clock, which is connected to the oscilloscope.
The rising edge of the 108MHz of the Transmitter is used for triggering the oscilloscope.
8.8 Complete drift compensation measurement
Figure 8.6: Temperature of the fiber spool during the whole measurement time of 2.5h.
The temperature changed from slightly less than 5 centigrades up to almost 15 centigrades resulting in 10 centigrade temperature difference.
of the FPGA based divider synchronization. In this way also this component is included in the measurement. Both clocks are connected to an oscilloscope, where the rising edge of the 108MHz clock of the transmitter is used to trigger the oscilloscope.
In this measurement, the fiber spool was experiencing a temperature change between slightly less than 5 centigrades up to almost 15 centigrades, which results in a change of almost 10 centigrades (affecting the propagation delay for both fiber connections in the same way). The temperature change can be seen in Figure 8.6. The resulting phase shift was observed by the phase detector on the transmitter and the drift compensation implementation is therefore adjusting the fine and coarse delay of the two delay components (the adjustment of each delay component can be seen in Figure 8.7). In this case a coarse delay adjustment of around 2ns was required. Also corrected, but not shown in the figures is the symmetry detection and correction as described in earlier chapters.
The final results can be seen in the oscilloscope screen shot shown in Figure 8.8. The 108MHz of the transmitter module used for triggering the scope is not shown. The acquisition mode of the oscilloscope was set to infinite persistence. The trace in the middle shows the region of the rising edge of the 108MHz of the receiver module. The gray slit-like rectangular box in the middle represents the part of the edge with the largest phase fluctuations and had therefore been chosen for determining the performance parameters. The peak-to-peak phase fluctuation during the whole 2.5h measurement time is 78.5ps. This includes short term jitter as well as the residual long term drifts. Additionally the histogram of the gray region is calculated and shown at the bottom. It shows a Gaussian distribution with a resultingσ of only 9.71ps as an estimation for the average residual phase fluctuation, which is perfectly fulfilling the related design requirements.
Figure 8.7: The resulting coarse delay corrections calculated by the drift compensation algorithm on the micro controller and applied to the delay components are shown over the whole measurement time (the fine delay adjustments are not shown). The adjustment results into almost 2ns coarse delay.
Figure 8.8: Screen shot of the oscilloscope measuring the over-all phase fluctuation. The trigger of the oscilloscope is the rising edge of the 108MHz clock provided by the transmitter module (not shown in the picture). The shown trace is the rising edge of the 108MHz clock generated by the receiver module (based on the internally recovered 1.3GHz reference and divided by 12 and synchro-nized by the synchronization process). The acquisition was set to infinite persistence. The histogram shown at the bottom was calculated based on the small slit in the middle of the screen and represents the widest part of the edge. The measured peak-to-peak variation is 78.5ps. The resulting σ of the distribution is about 9.71ps.
Chapter 9
Firmware
Except for the critical clocks, which are routed directly between the clock recovery and clock output buffer and driver circuits, a FPGA represents the central component of the timing system module. The Xilinx Virtex 5 FPGA in the case of the first generation timing system module and a Xilinx Spartan 6 FPGA in the second generation module implement the main functionalities. On the second generation module the optional mezzanine board, which provides most of the components for the three transmitter channels, includes an Atmel AVR 8 bit RISC micro controller for each channel. All of these complex devices require firmware in order to implement the functionality required for the timing system, this firmware is described in the following sections in more detail.
9.1 Configuration of integrated circuits on the module
Many of the integrated circuits used on this module are complex elements and require external configuration or at least allow monitoring of important parameters. The interfaces for these components are different: starting from analogue voltages (like the fine tuning input of the adjustable delay components), over binary digital (e.g. coarse delay configuration) and SPI and I2C protocols. The implementation of these interfaces differs slightly between the first and the second generation module. In the first generation module all components are located on the AMC module and the FPGA implements the communication interfaces. In order to generate digitally definable voltages and to reduce the number of digital lines to the FPGA, the first two interfaces are connected through another integrated circuit, which provides those signals (a serially programmable I/O component). This chip provides an SPI interface. Therefore all components are connected to the FPGA via serial communication on SPI and I2C protocols.
The firmware includes an implementation of these standards and allows the FPGA or a con-nected in-crate CPU to configure and read out all parameters.
In the case of the second generation module many components (related to the transmission of the timing data stream and drift compensation) are located on a mezzanine module. The configuration of those components as well as the later described drift compensation are imple-mented in the Atmal AVR micro controllers on the mezzanine board. Each micro controller provides a I2C interface to the FPGA and as all other components left on the AMC module only requires either I2C or SPI interfaces, no additional programmable I/O circuits are required. As in the first generation module, the FPGA implements interfaces to these serial protocols and provides full access to the in-crate CPU, as will be described later in this chapter.