Delay, CDR and clock dividers

Important aspects to be investigated are additive jitter, temperature dependent drift, deter-ministic phase relations, behavior at temporarily missing input signals and influence of data patterns compared to pure clock cycles.

In order to investigate the components (devices under test - DUT), evaluation boards for each of them have been bought from the manufacturers. The setup for investigation of jitter, drift and phase relations and behavior at missing input signal are depicted in Figure 5.1. In case of the jitter measurement (Figure 5.1(a)), the used signal generator (a data timing generator DTG5274 from Tektronix and SMA100A from Rohde und Schwarz) was connected directly to the signal source analyzer (E5052B from Agilent). The resulting phase noise spectrum were measured and the integrated jitter calculated and saved for future comparison. After that the different components (DUT) are connected, the resulting phase noise and integrated jitter could be determined. The results, compared to the pure source, represent a measure of the additive jitter and provides insights of deterministic noise components (if present and relevant).

The setup for drift measurements is shown in Figure 5.1(b). The SMA100A is used as signal source and connected to the DUT. Then the output phase is compared to the phase of the source without passing the DUT (in this case an evaluation board of the AD8302 phase com-parator from Analog Devices Inc. [38] has been used). In order to adjust the two phases at the comparator, a phase shifter has also been added. The output of the phase comparator is captured by an ADC (in this case a Voltmeter Fluke87) and saved over a longer time frame. In parallel a temperature sensor is attached to the DUT and captured and saved as well in order to correlate phase and temperature later on. In order to investigate the phase change based on temperature of the DUT, it is placed in an oven and temperatures between 20 centigrade and 25 centigrade are generated.

(a) Setup for jitter measurements. Initially the source is connectd directly to the signal source analyzer in order to capture and store the phase noise spectrum for later comparison. Then the DUT is included into the signal path and the resulting phase noise spectra measured and the integrated timing jitter calculated.

(b) Setup for dift measurements. The phase change over time and/or dependent on the temperature is detected by comparing the source’s direct signal and the one through the DUT. In order to set the initial phase at the detector to its optimal position, a phase shifter has been used. Phase detector output voltage is measured and recorded over time with a volt meter. Additionally, the DUT is placed in an oven along with a temperature sensor, which is also connected to the volt meter.

(c) Setup of the transient signal and data measurement. The source is connected directly to the oscilloscope as well as passing the DUT in order to compare the input and output of the DUT. Additionally the source generates a trigger in order to indicate special conditions to be investigated.

Figure 5.1: Three different types of measurements have been carried out: short term jitter, temperature dependent phase drift and transient/data signal behavior.

Finally Figure 5.1(c) shows the setup to investigate transient and deterministic behavior like start-up conditions, missing input signal, data pattern variation and phase relations. In this case the DTG5274 output is attached to an oscilloscope and the DUT in parallel. The output of the DUT is also connected to the scope in order to compare signals. Further more, the source will generate a trigger signal based on certain conditions to be investigated. This signal will be used to trigger the oscilloscope.

The results of the measurements are presented in the following table.

5.1 Investigation of critical components

Table 5.1: Results of the measurements of critical components. All components have been measured individually with dedicated evaluation boards from the man-ufacturers.

Adjustable Delay CDR Clock Divider Clock Divider

SY89296 ADN2812 LMK01000 AD9516

Additive Jitter^a <1ps <1ps 0.35-0.57ps^b 0.4-3ps^b Phase Drift 3.3-15ps/K^b 5ps/K 0.18-0.51ps/K^b 0.09-0.15ps/K^b

Deterministic Phase yes yes^c yes^c yes^c

Compatible to Data yes yes not applicable not applicable

aIntegration of phase noise between 10Hz and 10MHz.

bProportional to the configured delay.

cThe component has to be reset/synchronized after the input signal has been discon-nected or switched off and is then up again. Otherwise a different phase relation is possible.

The results show, that all investigated components provide a low additive jitter. Taking further into account, that the CDR includes a PLL with, currently not optimized, external loop filters, which allow jitter attenuation of the received timing signal, the chosen components will be suitable in terms of jitter requirements. Another important finding can be deduced from the drift measurements: The delay and CDR introduce a significant phase drift depending on temperature. Therefore the two supposedly symmetric delay elements should be tied together in terms of temperature (for example by using the same heat sink) and should experience only slow temperature changes in order to be able to compensate for them (e.g. using a heat sink and keep airflow stable). The temperature of the CDR should be kept constant as far as possible or phase correction based on measured temperature and a calibration table should be considered.

Furthermore the measurements revealed, that all components provide a deterministic phase relation between input and output, if a re-synchronization has been performed, after start-up or an input signal was missing. Therefore a signal detection (or signal loss detection) has to be implemented and used to reset or re-synchronize the related components. Finally it has been verified, that the delay element as well as the CDR are working properly with the type of data pattern intended for later data transmission.

5.1.2 Phase detector

The phase detector is intended to be used at three positions within the drift compensation scheme (see Figure 4.2): at the end of the full loop to compare the recovered phase with the reference and to compare the input and output phase of each delay component. In the first case both inputs of the phase comparator are always continuous clocks and they will be even kept at an phase difference of about 90 degrees by the drift compensation algorithm. How-ever, in the other case, the signal is the timing data stream and not a continuous clock. The measurement described here will investigate the influence of the signal pattern on the phase detector output and design consequences based on that. The setup for this test is the same as shown in Figure 5.1(c) The source was configured to generate arbitrary data patterns with a bit rate of 1.3Gbps. The phase detector measures the phase between input and output of the delay component (which was configured to a mid-range delay). The oscilloscope showed the output of the phase detector.

The result of this test was, that a wide-band and noisy signal is visible at the output of the phase detector and no phase relation can be determined. Repeating the same test, but with a

regular (clock-like) data pattern generated by alternating zeros and ones, the phase detector output provides low-noise and reliable phase relations.

This test shows, that a regular clock-like pattern has to be included in the data stream in order to reliably determine the phase relation between the input and output of the delay component.

This is feasible, as a valid clock-like data word in the 8b10b encoding table exists (D21.5) and the bandwidth required for the actual information to be transmitted is low.

(a) Photo of the Evaluation board. On the left side the SFP socket and SMA connectors provide a signal input and output interface. The center of the board implements all com-ponents required for introducing a phase delay, recovering the clock and measure phase errors. The right side implements supporting electronics for control and power supply.

(b) Simplified block diagram of the evaluation board. Only the components and con-nections, which are relevant for the described measurements are shown. Also supporting connections and components are omitted.

Figure 5.2: Evaluation board to investigate combinations of components used in the drift compensation scheme. The board was designed by A. Hidvegi from Stockholm University.