character. H5-12 is high and feeds into F4·6.
E5·14 feeds
into F4~7.The output
F4~5is
then inverted to make the RCV level.
HCS-220003 Section IV c. Off Line
The 1030 is designed to work as an office typewriter off line. When it is off line the Clear to Send level will be low. The output of the Input Buffer will be high. L5-14 will be low. With these levels present the Trans-mit and Receive gate will be gated off.
4-30. FREQUENCY DIVIDER AND SHIFT CLOCK
a. Transmit
1. Frequency Divider
In the 1 030 we have a need for a very stable Clock rate. This stability is quired for dependability in its re-sponse to codes. The clock rate is quite slow and a slow running Oscillator is not very stable. To gain stability we use a much higher frequency Oscilla-tor and divide it down to the Clock rate. The Oscillator ·runs at a frequency of 17 .227 KHz. This gives us a 58 mi-croseconds square wave out of the Os-cillator. The output of the Oscillator is fed into E1-3 where it is NANDED with Osei 1 lator Gate. E 1-2 output is then fed into the clock input of the first Frequency Divider flip-flop. When Oscillator Gate goes high F. D. Reset goes low for 10 microseconds and Sets each gate in the Frequency Divider to low at the Oscillator Frequency. 01-3 goes high. The low at 01-2 is
The reason the flip-flops do not con-tinue to transfer is because N8828A responds to the positive going edge of the clock pulse only. The Data inputs are locked out once the clock is high, thus preventing more than one tran-sition of the binary per clock pulse.
01 -3 clock input goes high again. The high that is now at 01-2 transfers to 01-5. 01-5 goes low, 01-6 goes high.
Now 01-9 will change states because its clock input is high. This procedure takes place throughout the Frequency Divider causing D5 to toggle at a 7.43 millisecond rate.
2. Shift Clock
The purpose of the Shift Clock net-work is to provide a 116 microsecond Clock pulse every 7.43 milliseconds.
05-6 is NANDED with E4-11. E4-11 center of the bit of information. To do this the true side of D5 is NANDED with the
Receive Control Level. The output of E4 then follows the same path as in transmit.
4-31. FREQUENCY DIVIDER CONTROL a. Transmit
The Frequency Divider Control is used to turn the Clock on and off. F3-5 will go low and cause F3-2 (Oscillator Gate) to go high.
Oscillator Gate must be held high for 67 milliseconds. F3-4 will go low for 7.43 milliseconds. F3-6 will go low for 66.87 milliseconds. F3-3 will go low for each Clock· pulse. Clock holds the output high between F3-5 going high and F3-4 going low. F3-2 is Oscillator Gate. It is fed into E2-3. E2-3 is ANDED with the Oscillator Gate which has been delayed 10 micro-seconds. E2-2 is F. D. Reset. E2 is an SP659A because of the heavy load it must drive.
b. Receive
The Frequency Divider works the same in receive as in transmit except for 1 signal level. F3-5 stays high all the time in receive.
F3·4 will go low and turn Oscillator Gate on. F3-3 and F3-6 will keep it on for 66.87
4-65
Section IV HCS-220003 milliseconds. Oscillator Gate and F. D.
Re-set
operate the same as in transmit.4-32. PARITY GENERATION AND DETECTION
a. Transmit
Parity Generation is accomplished with a control gate, flip-flop and an extended NANO Gate. The control gate NANDS Shift and Transmit Control Level with Start from the Serial Data Register. E5-6 will be used as a Clock input for the Bit Counter.
A "1" is loaded into the Serial Data Regis-ter. E5-7 will go high for 66.87 milliseconds because of actual transmission of a charac-ter. E5-10 will go high with the Shift pulses.
E5-9 will be low. Therefore, when the Shift pulse comes in on E5-10 the output of E5 will remain high. D5 was put in the reset condition by S. R. Reset and will remain in that condition until the Clock input goes low and back high. E5-9 will stay low until after receipt of the 6th Shift pulse. The 6th Shift pulse comes in to E5. The output does 66.87 milliseconds. E5-9 goes low with S. R. Load as the Serial Data Register is·
loaded for the letter "F". 7.43 milliseconds later E5-10 goes high for 116 microseconds.
E5-6 does not change because E5-9 is low.
The Shift pulse on E5-10 goes low. E5-9 goes high. 7.43 milliseconds later E5-10 goes high. E5-6 goes low for 116 micro-seconds then back to its high state. As E5-6
goes high 05 changes states. D5-9 is now high. The 3rd Shift pulse comes in on E5-10. E5-6 goes low for 116 microseconds then back to its high state. As E5-6 goes to the character at this time. L4-14 will de-termine if we have a Check bit or not. The 10 inputs that control L4-14 are setting at these levels now: E3-3 low, E3-4 high,
L3-12 high, L3-13 high, L3-10 high, L3-11 high, l4-10 high, L4-11 high, L4-12 high, L4-13 high. One input is low, therefore, L4-14 is high and a Check bit wi 11 be added.
b. Receive
Parity Detection is accomplished with a control gate and a bit counter. Receive Control Level is NANDED with Serial Data
Receive to the Serial Data Register and Shift. Receive Control Level on E5-3 will go high and stay high 66.87 milliseconds. Se-rial Data Receive on E5-5 will go high and low with the character signals received.
Shift on E5-4 will go high for 116 micro- · seconds once every 7.43 milliseconds for 8 times. S. R. Reset comes in on D5-13 reset-ting 05. 05-9 is now low. Each time Serial Data Receive and Shift are high at the same time, E5-2 will go low. E5-2 goes low for
116 microseconds then back high. Each time E5-2 goes high D5 will change states.
D5-8 is the Parity signal.
4-33. SERIAL DATA REGISTER EMPTY a. Transmit
1. Serial Data Register Empty
Serial Data Register Empty is the sig-nal used to tell the Serial Data Regis-ter Cycle Control that the Serial Data
HCS-220003 Section IV Register is completely empty. One
in-put from each flip-flop of the Serial Data Register comes into the Serial Data Register Empty extended NAN D gate and its expanders. Following the 8th Shift pulse the Serial Data Regis-ter Flip-flops will all have their Q side high except for Start, it will have Q high. When this condition is present Serial Data Register Empty will go low indicating that the register is empty.
L4-2 is then inverted in J1 to make Serial Data Register Empty.
4-34. LINE DECODER a. Receive
1. Line Decoder
The Line Decoder converts Line Code into Latch Code. The information is loaded into the Line Decoder in para I·
lei. The information is then NANDED with P.R. Load.J5'(pins9, 10,& 11) converts B into T2 Load. J5 (pins 12, proper inputs to either gate will give us R-5 Load. The output must go low for that information to be loaded into the Print Register.
4-35. LINE ENCODER a. Tn;insmit
1. Line Encoder
The Line Encoder is used to convert latch code into Line Code. The Print Register outputs are NANDED with S. A. Load to give us Line Code to be loaded into the Serial Data Register.
N2 (pins 5, 6,
&
7) convert R2A into don't load those bits into the Serial Data Register.4-36. SWITCH ENCODER AND PRINT REGISTER
a. Transmit
1. Switch Encoder
The Switch Encoder converts Bail Switches, Operational Switches and Control Modes into Latch Code for the Print Register. All Switch Encoder inputs will set normally high and go low. The output will be normally low.
There are 6 groups of Switch Encoder Gates, one representing each of the baits in the printer. When a character is selected from the keyboard and T2 Bail Switch closes R5-14 output will go high. R5-14 is NANDED with Key-board. R4-5 output feeds into R4-13, the T2 Print Register latch. When an operation is performed its ~witch ter-mination is fed into the proper gates to give us the code we need. The code for Space is T2, T 1, R 1, A2, and R2A·
Space Switches termination is fed into T2 Switch Encoder, T 1 Switch En-coder, R1 Switch EnEn-coder, R2 Switch Encoder and R2A Switch Encoder.
R2 Switch Encoder Gate has all of the operational switches coming into it so its output is called Switches and is used to set Switch Pulse Pulse Delay.
2. Print Register
The Print Register is basically a storage and buffer unit. The Print Register is the only place in the logic that Code is held until the next character comes in.
The outputs from the Switch Encoder are fed into the true side of each bail latch. Register Reset is fed into the false side of each Print Register latch.
Each Print Register latch is made up 4-67