from logic, the desired solenoid (tab, space, back-space, carrier return, and index) is energized and the appropriate operation is initiated.
4-20. SWITCHES
BAIL SWITCHES - Six Reed switches which are actuated by the latch interposers (R1, R2, R2A,
R-5, T1, and T2) for encoding to the logic.
OPERATIONAL SWITCHES - The tab, space, backspace, carrier return, and index switches en-code the information sent to the logic to indicate the operation being performed.
FILTER SHUTTER - A reed switch and bow tie shaped vane are operated by the rotation of the filler shah. A pulse is generated by the switch and sent to the logic as a strobe (LE) and a busy signal (TE) to control cycle time.
SHI FT SWITCH - A micro switch sends a signal to the logic to indicate a case change to upper case .
...
SHIFT INTERLOCK SWITCH - A reed switch operated by a vane which folfows the shift cam in-dicates when the shift cycle is complete.
4-21.
TRANSMITThe switches are used when the terminal is in a transmit mode. A switch changing state indicates two things to the logic.
a. Tells the logic that we are beginning to transmit a character.
b. Tells the logic what character to transmit.
When we transmit an operation one switch does both a and b above, but when we transmit a key-board character we rely on two switches. Filter shutter performs function a alone, while we use the bail switches to perform function b.
Filter shutter also tells the logic when to look at the bail switches. Its timing with regard to the bail switches is very critical. This timing relationship will be covered in Section V.
4-22.
RECEIVEThe receive section of the interface consists of mag drivers and solenoids. One mag driver circuit for each solenoid. When the logic receives and
de-codes a character low going pulses are sent to the interface (in parallel) to turn on the mag driver(s) needed for that character.
The low going signal is input to base of the PNP transistor of the mag driver circuit (2N
4125).
That transistor "turns on". When it "turns on" the level at the base of the NPN transistor (2N3569) goes more positive and causes that transistor to "turn on". As long as we hold the input to the mag driver circuit low both transistors will be "turned on".This "turn on" will apply a ground potential to one side of the related solenoid. The other side of the solenoid is connected to +24 volts. When the ground potential is applied we complete (or close) the circuit and current will flow through the coil, causing the armature to be attracted to the sole-noid. As the armature moves it will operate a me-chanical device in the 1/0 printer and initiate a me-chanical cycle.
4-23. LOGIC.
The logic is located on a single interchangeable board and consists of Transistor to Transistor Logic (TTL integrated circuits) and some discrete compo-nents. The Logic board must be supplied voltage from an external supply. Its requirements are +.5 volts and ±12 volts. The TTL integrated circuits have an operating voltage of
+5
volts which may be found on pin 8, ground may be found on pin 1 of every600
series IC. All other IC's have+5
volts on pin 14 and ground on pin 7. Signal levels on the logic board are+5
volts= HIGH and0
volts= LOW.The +12 volts operate discrete components on the board.
4-24.
INTEGRATED CIRCUITS (Signetics Spec.Sheet) used in the Collector logic configura-tion. A capacitor may be connected to the node pin to increase the turn on time. The Fan-In Expander SP631A is connected to the node pin when addi-tional diode inputs are needed.
HCS-220003 Section IV b. Expander Gate
1. The SP631 A is a Quad 2 input
Gate Expander used with the SP616A or SP659A to expand their input capa-bilities.
c. Buffer Driven Element
1. The SP659A is a Dual 4 input Buffer Driven NAN D Gate with an expander node. It is capable of driving a heavy load.
d. J-K Binary Element
1. The SP620A is a DC-Triggered master-slave, J-K Flip Flop. The circuit may be set or reset synchronously with the So and Ro inputs with the clock line low. The circuit may also be switched synchronously using the J and K in-puts with a clock pulse.
e. D-Flip Flop
1. The S8828A is a Dual Delay Binary Element which responds on the posi-tive going edge of the clock pulse. The logic level at the D input prior to the clock pulse will be transferred to the Q output with the rising clock pulse.
The So and RD are activated by "O"
level. A "O" at So causes Q output to go to "1" A "O" at RD causes Q out-put to go to "1 ".
f. Single Shot
1. The S8162A is a Nonstable Multivi-brator which can provide delays from 80 nanoseconds to 2 seconds by using the appropriate external components.
Pin 9 must be low when pin 10 goes low to get an output on pin 4.
g. Truth Tables
A Truth Table is an orderly array of all pos-sible combinations of inputs, together with the truth value of the resulting output. The Truth Table is shown in figure 4-154.
4-25. BASIC LOGIC FLOW a. Transmit
1. Bail Switch or Operational Switch actuated
2. Control Logic starts functioning 3. Load into Print Register
4. Load into Line Encoder
5.
Load into Serial Data Register 6. Parity Generation7. Output Buffers
INPUTS OUTPUTS OF THE IC NAMED
EXCLUSIVE EXCLUSIVE
A
B
AND NAND OR NOR OR NOR0 0 0 0 0
0 0 0
1 01
0
0 1 10
1 01
0
0 0Figure 4-154. Truth Table
4-61
Section IV
HCS-220003b.
Receive the start gate the inf<2!_mation is taken outin parallel as soon as Q of the start gate goes
1. Input Buffers high.
2. Control Logic starts functioning
4-27.
SERIAL DATA REGISTER - SHIFT CONTROL3.
Loaded into Serial Data Registera. Transmit 4. Parity Detection
In transmit we must have 4 signals at the
5.
Line Decoder same time to aet a shift pulse. Cycle,Trans-mit, and S. R. Empty go high and will stay 6. Loaded into Print Register high for 67 milliseconds. The clock pulse
goes high for 116 mi Iii seconds once every 7. Loaded into Mag Driver Decoder 7.43 milliseconds for a total of 9 clock
pulses. These 4 signals are ANDED together 8. Loaded into Mag Driver in gate J2. It is inverted in the same gate.
When all 4 inputs are high at the same time 9. Performs proper mechanical operation we then get a low out. This will fall at a
clock rate. The output of J2 is collector
4-26.
SERIAL DATA REGISTER OREO with H2. H2 will always be highwhile J2 is operating. J2 output is then fed
a. Transmit into J1 and inverted. The output of J1 is
Shift. We then feed J 1 into L5 and invert it The Serial Data Register is made up of four again. This is the SHI FT line that is fed into S8828A Dual Delay Binary Elements. S. R. the Serial Data Register Clock input. An
Reset is fed into the set input of each flip SP659A is used here because of the heavy flop. This drives the Q output high. The in- load.
formation is loaded into each flip flop at the
reset input in parallel. lf a one (1) is to be b. Receive loaded into the register the reset input will
remain high. For all bits that are not to be In receive we must have 3 signals at the loaded into the register the reset input for same time to get a shift pulse. RCV and that flip flop will go low and the
0
output START go high. Start remains high for will go low. When the register has been set 55.72 milliseconds. RCV remains high for arid reset according to the proper code the 67.43 milliseconds. Clock goes high 3. 71 SH I FT pulse comes into the clock input of milliseconds after RCV goes high and stays each flip flop and shifts the information out high for 116 microseconds once every 7.43serially. milliseconds thereafter for a total of 8
times. These 3 signals are ANDED together
b. Receive in gate H2. It is inverted in the same gate.
When al! 3 inputs are high at the same time In the receive mode the leading edge of the we get a low out. This will fall at a clock start bit is what starts the logic in motion. rnte. The output of H2 is collector OR ED As Serial Data Receive goes high these sig- with J2. J2 will always be high while H2 is nals are set: Start Time, Cycle, Oscillator operating. H2 output is then fed into J1 and Gate, F. D. Reset, S. R. Reset, Clock, and inverted. The output of J1 is Shift. We then Shift. Serial Data Receive is fed into the D feed J1 into L5 and invert it again. This is input of the register and K2·2 goes low. At the Shift line that is fed into the Serial Data the same time S.R. Reset goes low for 10 Register Clock input.
microseconds and is fed into the set input of each gate. This sets all Q outputs high.
3.71 milliseconds after the leading edge of
4-28.
SERIAL DATA REGISTER - CYCLE the start bit, we receive the first shift pulse CONTROLand then one every 7.43 milliseconds for a
total of 8 pulses. When the start bit reaches a. Transmit
HCS-220003
1. Cycle
The cycle latch is made up of 2 gates, J3 (SP680A) and H2 (SP670A). Be-fore a cycle starts the inputs should be set at these levels: J3-3 high, J3-4 high, H2-3 high, H2-4 low, and H2-5 high.
J3-3 is high because of the proper in-put levels to H2. J3-4 is high because F2 (SP620A) Start Time flip-flop is in the reset condition. H2-4 is low be-cause J3-3 and J3-4 are at the proper levels. H2-5 is high because Link Ready is high. H2-3 is high because H1-2, H1-6, and F1-14 are high. Gate H1 (pins 2, 3, 4, & 5) is used to gen-erate Stop Time in the transmit mode. Gate H1 (pins 6, 7, 9, & 10) start the timin·g of a cycle. Start Time is generated in Gate F2. F2-4 and F2-11 inputs are used in receive and will remain low in transmit. S. R.
Load comes in on F2-5 and sets Start Time. This causes Start Time to go low. Start Time comes in on J3-4 after Start Time goes high.
To turn the Cycle off after 66.87 milli-seconds the Stop Time signal, which is fed in on H2-3, must go low. Gate H1 (pins 2, 3, 4, &5) will do this in trans-mit. H 1-3 will go high at the beginning of the cycle and remain high for 66.87 milliseconds. H1-4 will go high when the check bit reaches the start gate.
H1-5 is the Clock line. When these 3 inputs are high at the same time, and only then, we will get a Stop Time pulse to turn the Cycle off.
Start Time, Transmit and Cycle are fed into J4 and NANDED together to
Section IV
ensure that the Data input to the Se-rial Data Register will remain low dur-ing the transmit cycle.
2. S. R. Load
S. R. Load is used mainly to load the Serial Data Register during transmit.
S. R. Load is generated by NAN DING 2 signals and inverting it again. Gate E 1 (pins 9, 10, & 11) is used for this.
Cycle comes in on E 1-9. Cycle is high because a cycle has not been started yet. KEYBOARD READY comes in on E1-10 and goes high. When E1-9 and E 1-10 are both high at the same time output E1-11 will go low. E1-11 isS. R. Load. E1-11 is then fed into E1-12, the output E1-14 is inverted.
E1-14 is S. R. Load.
3. S. R. Reset
S. R. Reset is used to set the Serial Data Register flip-flops and reset the Parity flip-flop. E 1-11 come in on inputs are high at the same time out-put E 1-5 goes low. E 1-5 is fed 2 places, straight into E2-12 and into a 10 mi-crosecond delay network. The delay network is made up of a SP616A with a capacitor connected to the node pin.
The output of the delay network F 1-2 is fed into E2-13. With this delay net-work operating properly we will get a 10 microsecond pulse out on E2-14.
E2-14 is S. R. Reset. Once again we use an SP659A because of the heavy load it is required to drive.
4. Parity Bit Injection and Interrupt Injection
The Parity Bit is injected into the char-acter after it has been shifted from the Serial Data Register. Start, Transmit, and Cycle are NANDED together.
Parity Bit is collector OREO to this output. This is the first time we have a complete character. This output is NANDED with Interrupt which is
nor-4-63