I SIMM3_ID I SIMM2_1D I S1MM1_1D I SIMMO_ID I

Main Memory Unil Sun-4D Architecture

5.3.5 Group Type Registers

There are two pseudo-registers that identify the type of SIMMs plugged in each / ,

Pqe94

group. These registers are read-only, and are accessible as double-words. '.,~

The structure of the Group Type registers is the following:

I

^SIMM3_ID

I

^SIMM2_1D

I

^S1MM1_1D

I

^SIMMO_ID

I

63 48 47 32 31 16 IS 0

where:

SIMMII_ID: ldentifierofSIMM 11. An 8-bit identifier is hardwired on all SIMMs used in SunDragon to make them self identifying. During system initialization, the Group Type registers must be accessed to determine what type of SIMMs are plugged in each group. The identifiers can be used to retrieve the size and timing characteristics of the groups by accessing a table in EEPROM or NVRAM.

The format of the SIMMn_ID fields is the following:

I

^10[7:6]

I

^Un

I

^10(5:4]

I

^Un

I

^ID[3:2]

I

^Un

I

^10[1:0]

I

^Un

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

o

The bit fields have the following ~aning:

Un: Undefmed. These bits are undefined.

ID[7:0]: SIMM Identifier. There are two encoding of this field; one for regu-lar DRAM SIMMs and one for NV _SIMMs.

DRAMSIMM:

With DRAM SIMMs the encOding of the identifier is' the following:

, . 0 Manit!' Speed

I

^Size

7 6 4 3 2 1 o

For the two CUJTent suppliers of SIMMs for SunDragon (Mitsubishi Semiconductor and Texas Instruments) the bit fields have the following meanings:

Size: The encodinl for the size is:

Size DRAM Size

00 4M-bit

01 16 M-bit 10 64 M-bit 11 256M-bit

Speed: The speed is relative to the size and' the manufacturer field. For the first SIMMs developed by Mitsubishi and Texas Instruments with 4 M-bit DRAM the encoding and the corresponding value for the Refresh Count and Request Delay

San/Xerol Private Data 9/10192 - Rev 1.4

(

\" /

(

I I

9/10192· Rev 1.4

Sun4D ArchH.ecture Mam \iemor;. L nIl

is:

Speed Access Time

ReNT RDLY

00 SOns 0010012 00102

01 lOOns 0010012 00112

10 Reserved Reserved Reserved 11 Reserved Reserved Reserved Manftr: SIMM Manufacturer code. The encoding is:

Manfr Manufacturer

000 Reserved

001 Mitsubishi Semiconductor 010 Texas Instnlments

011-111 Reserved

NOTE: An access co the Group Type register causes an extra refresh cycle of the group's DRAMs NOTE: If no SIMMs are present in a given memory group the vaiue 0xFFFF FFFF FFFF FFFF is

returned on a read of the Group Type regis&er. The memory group must be disabled by set-ling the SSIZE field to 0002 in Ihe corresponding Address Decoding regis&er.

NOTE: It is possible to mix SIMMs of different manufaclUJa'S inside the same group provided they are of the same size and have ihe same timiDI characteristics. This implies the four half-word of the Group T.ype registers may have different values.

NV SIMM:

With NV _SIMMs the encoding of the identifier is the following:

1

I

^BS

I

^{Manftr . Speed}

I

^Size

I

1 6 'S 4 . 3 2 ₁

o

The bit fields have the following meanings:

BS: Battery Status. This bit is one is the battery is in good condition and

zero if the battery failed.

Size: The encoding for the size is:

Size SRAMSize 00 1 M-bit 01 4 M-bit 10 Reserved 11 Reserved

Speed: The speed is relative to the size and the manufacturer field. For the rU'St SIMMs developed by Mitsubishi with 1 M-bit SRAM the encoding and the corresponding value for the Request Delay is:

Speed Access Time

RDLY

00 'Ons 00112

Sun/Xerox Privaae DIla ^{Page 95}

1 I I I I I I I I

Main Memory Unit Sun4D Architecture

Speed Access Time RDLY

01 SSns 00112

10 Reserved Reserved 11 Reserved Reserved Manftr: SIMM Manufacturer code. The encoding is:

Manfr Manufacturer

00 Reserved

01 MiuubuhiSenriconducttr 10 Reserved

11 Reserved

5.3.6 Memory Control and Status Register

The Memory Control and Status Register is used to implement the address inter-leaving decoding. This register may be read and written as a double-word.

The Memory Control and Status Register has the following structure:

63 18 17 16 i3 12 7 6 2 1 0

The various bit fields have the following meaning:

Rsvd: Reserved. Reserved fields are ignored on a write and read as zero.

RFEN: Refresh Enable. When this bit is zero, the DRAM chips are not re-freshed. This bit is not affected bY'system reseu. but is cleared when INIT is assett- """

ed (See deScription otINIT on page 9S). See section S.S.1 on page 109 for a description of the MQH reset sequence. This bit must be set to one if at least one of . the active memory group consisu of regular DRAM SIMMs. An active group is a

group for which the SSIZE field in the Address Decoding register is not null. If all active groups are composed of NV _SIMMs. it is not necessary to enable refresh as they are composed of SRAM memory chips. An inactive group (group for which the SSIZE field is null) is not refreshed even it RFEN is set to one.

NOTE: DRAM c:bips must requires eiPt refresh cycles before being accessed. This condition can . be saIisfied duoup. software delay or by reading the Group Type regisler eight times (See

IOCIiaD 5.8.1 on ^pile 109 for. description of die MQH initialifalion).

RDLY: Request Delay. This field contains the number of Dynabus cycles the MQH must wait. from the beginninl of the memory access, before issuing a bus request. It is used by the MQH to overlap the memory access with Dynabus arbitta-tion when a 64-byte subblock is read. This parameter depends of the access time of the memory and the minimum request to grant delay of the Dynabus arbiaation 101-ic. See section 5.3.4 on page 93 for the predefined values of RDL Y for the Miuub-ishi and Texas Insttumenu SIMMs and for the Miuubishi NV _SIMMs. If one or multiple NV _SIMM groups are mixed with one or more regular DRAM SIMMs

Sun/Xerox Private Daaa 9/10192 -Rev 1.4

/ '

(

[-RCNT

Sun-4D Architecture MaIn Memory C nil

groups then, the NV _SIMMs RDL Y value must be used. The SIMM Request De-lay value must be used only if all memory groups are composed of regular DRAM SIMMs.

RCNT: Refresh Count. This field defines the refresh period minus 1 in mul-tiple of 64 Dynabus clock cycles. The refresh period is: (RCNT + 1)· 64·2Sns. The minimum refresh period is 1.6 ~s (RCNT~) and the maximum refresh pe-riod is 102.4 J.LS (RCNT = 1111112)' The actual period at which DRAM chips receive refresh cycles depends of the number of active memory groups. An active group is a group for which the SSIZE field in the Address Decoding register is not null. ^If only one group is present it receives refresh cycles at the rate defined by the RCNT value. If N memory groups are presents (N=2,3 or 4) then the DRAM receives re-fresh cycles at l/Nth of the rere-fresh period defined by RCNT. The following table defines what value of ReNT should be used for the current SIMMs with a 40 Mhz Dynabus clock:

One Group Two Groups Three Groups Four Groups

MQHIMQHP MQHIMQHP MQHP MQHP

Mitsubishi 0010012 0001002 0000112 0000102

RCNT TI

9/10/92 - Rev 1.4

0010012 0001002 000011 2 0000102

NOTE: 'Ibe value of RCNT depends on the number of acave memory groups only and not of the

type of the memory groups. If NY_SIMMs groups and regular DRAM SIMMs groups are connected ro the same MQH. then it is the rotal number of groups which determines the val-ue of RCNT. For inswtce. if an MQHP supportS two replai- SIMM groups along with an NY _SIMM group. then RCNT must.be set lP OOOO~ 1_2, . '

NOTE: . If the system is ^~ng with a Dynabus clock frequency which is smaller than 40 Mhz. the RCNT value must be scaled accordingly.

The value of the Refresh Count is not affected by system resets, but it is cleared when INn'is assened (See description of INIT on page 98).

ECI: Enable Correctable Error InteJTUPt. When this bit is set to one, a lev-el IS interrupt is broadcast when a correctable error is detected and no previous er-ror is pending in the ~orrectable Error Address register (i.e. the ME and SBE bits are clear in the Correctable Error Address register). If this bit is zero no interrupt is broadcast but the error is still logged in the Correctable Error Address and Data reg-isters (See section 5.5.3 on page 106).

DMPR: Demap Reply Enable. When this bit is set to one, the MQH issues a DemapReply packet on Dynabus whenever a DemapRequest is ~eived [4]. When this bit is clear, DemapRequest packets are ignored. On a given Dynabus, one and only one MQH must be configured with this bit set to one for the Demap mecha-nism to work properly. The address filtering logic is bypassed for Demap packets.

Sun/Xerol Private Data Page 97

M.aJn Memory l"mt

5.4 Oynabus Registers

5.4.1 ComponentlD Register

This register is read-only. It is accessible as a word.

The ComponentID Register has the following structure:

Version

I

^{PartID ManflD 11}

I

31 28 27 12 11 1 0

The various bit fields have the following meaning:

Version:

PartID:

4 bit version number. Set to Oxl.

Pan ID. 16 bit pan number.

ManrID: Manufacturer ID. 11 bits Sun JEDEC Identifier. Set to Ox03S.

The following PanICs and versions are currently legal:

PartID Version ComponentlD Component

OxOADC 1 Oxl0ADC07D MQH

OxOD86 1 Oxl0D8607D MQHP

5.4.2 Dynabus Control and Status Register

Pap 98

This 64-bit register contains certain Dynabus parameters which must be loaded via

IT AG after a power-on reset. It is also used to record when a fatal error is detected by the MQH. A fatal error is an error which causes a system watchdog reset (See . Chapter 7).

. .

This regist.et: is accessible as.a double word.

. .

The Dynabus Control and Status Register has the following:

Im Dokument Sun-4D Architecture (Seite 106-110)