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Sun-4D ArchiteCture Processor Unit
FlI_X Sub·block State S Shared. Not Owner. Retry 6 Shared. Owner. Not Retry 7 Invalid
Not Shared means that there are no copies of the sub-block in other processor cach-es. Shared means that there may be copies in the caches of other processors. Owner means that the sub-block was modified last by the attached processor. Retry means that a Read Block Dynabus transaction issued by this BW must be retried. For more details on the cache consistency protocol. the reader may refer to [4].
The Flags must be initialized by software after a power-on reset All tag entries must be written with the value 0 x 7 FFE 0000.
T A: Tag Address. This bit field has the following structure:
PA[3S:19]
16
o
Note that all bits of TA are significant. independently of the configured External Cache size.
ComponentlD Register
This register is read-only. It is accessible as a word.
The ComponentlD register has the following structure:
Version
I
PanID ManfID31. 28 27 12 11
The various bit fields have the following meaning:
Version: 4 bit version number.
PartlD: Pan 10. 16 bit pan number.
1 0
ManfID: Manufacturer ID. 11 bit Sun JEDEC Identifier. set to Oz03Z.
The followinl PartlDs and versions are cumndy lelal:
PartJD Version ComponentID Component
OdDB 1 Oz10ADB07D BW,lKTags
OdDB 2 Oz20ADB07D BW, lK Tags
OzD3' 1 Oz10D3'07D BWP,4KTap
There is no functional difference between both versions of BW. The first version contains some loaical bUls which are fixed in the second version. Only the second version will be shipped but the first version may be used for system brinl-UP.
Dynabus Control and Status Register
This 64-bit repster contains cenain Dynabus parameters which must be loaded via IT AG after a power-on reset. It is also used to record information when a fatal ere
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ror is detected by the Bus Watcher. A fatal error is an error that causes a system watchdog reset (See Chapter 7).
This register is accessible as a double word. It is also accessible via JT AG as part of shadow scan chain 0 (See section 10.3.4 on page 184).
The Dynabus Control and Status register has the following structure:
where:
Rsvd: Reserved. Reserved bits are ignored on a write and read as zero.
ITO: Test Time-Outs. When this bit is set to one, the time-out period in-dicated by the GTOL and RDTOL fields is divided by 1024. When this bit is set to zero, the time-out periods are computed normally. In normal operation, this bit must be set to zero. This bit is read-only.
TSel: Test Selector. This field indicates the test mode seiected when TM is one. This field is read-only.
TM: Test Mode. When this bit is set to one, the chip verification test mode defmed by TSel is enabled. When this bit is zero, the chip operates nonnally.
This bit is read-only. It must. be set to zero except for chip manufac~g test TLD: Top-Le~el Device. This bit must be set to zero if there is a second-level Dynabus cache above this BW in the Dynabus hierarchy. It must be set to one otherwise. In normal operation on CUJTent Sun-4D systems, this bit must be set to one through JTAG. This field is read-only. See [4] for details on the effect ofTLD.
EER: Enable Error Reset If this bit is set to one, any fatal error detected by the Bus Watcher causes a system watchdog reset If this bit is set to zero when a fatal error is detected no system watchdog reset is issued. However, the error infor-mation is lOlled nonnally. This bit is read-only.
SOLat: SharedIOwner Latency. Latency in number of Dynabus cycles from the time an address appears at the input pins to the time the Shared/Owner signals are asserted at the output pins, minus 2 (See[4] for more informations on Dynabus).
This field is read-only. In normal operation on current S un-4D systemS, this field must be initiaJized to Ox2 (corresponding to a 4 cycle Shared/Owner latency) throup TrAG. Note that BW will not function prOperly if a value lower than Ox2 is used.
DNum: Dynabus(ses) Number - 1. Number of active Dynabus(ses) in the system minus one. This field is read-only. It is initialized through JTAG.
Dlndex: Dynabus Index. This field indicates the number of the Dynabus to which this BW is connected. This field is read-only. It is initialized through JTAG. ,)
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DeviceID: Oynabus DeviceID. This field is read-only. It is initialized through IT AG. In current Sun-40 system the four most significant bits of this field must conespond to the board number.
FZN: Frozen. This bit behaves as if reserved on CSR space accesses (i.e.
writes have no effect and reads return zero), but it is accessible via JTAG (See sec-tion 10.3.4 on page 184). FZN is set to one on a system reseL When FZN is one, BW remains in the reset state and can only be accessed using ITAG.
ErrLog: Error Log. This field is used to log the parity bits when a Oynabus parity error is detected. The 8 parity signals compute byte parity over the 64 Oyna-bus data signals. The position of the parity bit determines the byte it protects. The least significant bit protects the least significant byte of the data signals and so fonh.
The parity can be odd or even according to the type ofOynabus cycle (See [4] for more information). The Err Log field is also used to log the value of the seven Board Arbiter lines when a parity error is detected on these lines. In this case, the structure of this field is the following:
I
Rsvdl P I BGnt IOwnl Shdl GntType I7 6 5 4 3 2 0
The bit fields have the following meaning (see [9] for a detailed explanation of the arbiter signals):
Shared. Logical OR of the Shared lines.
. Owner. Logical OR of the Owner lines.
. Board Grant.
P: " Even"Parity on the arbiter lines.
Rsvd: Reserved. Read as zero and ignored on a write.
This field cannot be written, even through JT AG, as long as fields GTO, GPE, OPE, CDE are nonzero.
NOTE: When a Dynabus parity error is delect.ed during the very same cycle where FZN is cleared.
the errar is delect.ed and recarded c:orrecdy (OPE is set to one) but the parity bits are aot
Iaaed in abe ErrLog rleld. The correct initialization sequence which guanncees that the
parity bilS are logged conect1y is detailed in section 405.10 on page 71.
Eel: Enable Count The value of this field specifies the type of events which are counted in the EC field of the DynaData register if there is no pending fatal mor. It is readable and writable. The encoding is the following!:
ECf
Type of Events Counted0 Counting Disabled
1 Nbr of cycles Pause has been assened 2 Nbr of shared writes from this BW 3 Nbr of subblocks flushed by this BW 4 Nbr of cycles waiting for read miss reply
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ECT Type of Events Counted
5 Nbr of write-update cycles to CC (WS+WB) 6 Nbr of requests for owned data (RB) to CC 7 Nbr of writes to non-shared. non-owner subblock
GTOL: Grant Time-Out Lo&-Value. This field specifies the Grant Time-Out counter value in log base 2 of 1 K Dynabus clock cycles (the time-out period is divided by 1024 if bit ITO is one). This field is readable and writable. A Grant Time-Out is reponed if the arbiter does not allocate the bus N Dynabus cycles after a bus request was issued. The Bus Watcher implementation guarantees that:
2 (lO+OTOL) < N < 2*2 (lO+OTOL).
RDTOL: Read Data Time-Out Lo&-Value. This field specifies the Read Data time-out counter maximum value in log base 2 of 1 K Dynabus cycles (the time-out period is divided by 1024 if bit 110 is one). This field is readable and writable.The BW suppons three different time-out schemes (in the following, RDTO denotes a time equal to 2 (lO+RDTOL»:
• A time-out is reported if a demap (MMU flush) has not completed N Dynabus cycles after it was issued (See section 4.2.3 on page 36 for a description of demap in Sun-4D systems). The implementation guarantees that
8*RDTO < N < 16*RDTO.
• The second scheme is used for all Dynabus requests except WriteSingle and 10-Write ttan~ons (See [4]). A time-out is reponed if no reply packet of the same type" is ~ived N J;>ynabus cycles after a request was issued The Bus Watcher implementation P,arantees that RDTO <; N < 2*RDTO.
• The " third scheme guarantees that all issued WriteSingle and 10Write requests get a reply. A WriteSingle request is issued when the processor writes a shared variable in Memory Space. An 10Write request is issued for a write in I/O Space. The Sun-4D systems Memory Model (See Chapter 2) implies that mul-tiple StoleS in Memory Space and I/O Space can be pending.
In Total Store Ordering mode, a processor must wait for the completion of each write to a shared variable. In this case, a time-out is reponed if no reply packet is teeeived N Dynabus cycles after a WriteSingle was issued.
In Partial Store Ordering mode a processor must wait for the completion of pendinl writes to slwed variables only when a STBAR is executed (See section 2.4 OIl pap 16). In this case, a time-out is reponed if all WriteSingle reply pack-ets have not been received N Dynabus cycles after the last WriteSingle request
was
issued.The Bus Watcher implementation parantees that RDTO < N < 2*RDTO.
Multiple
JJO
stores can be pending as long as they are directed to the same Dynabus and reference the same page. The processor must wait for the comple-tion of theJJO
store either when a STBAR is executed or when an I/O store is1. Refeoz ~ the Dynabus speciflCalion [4] lei' more details on Dynabus nnsaclions
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directed to a different page or Oynabus. In this case, a time-out is reponed if all IOWrite reply packets have not been received N Oynabus cycles after the last IOWrite was issued.
ME: Multiple Errors. This bit is set to one when multiple fatal enors have been detected. This bit is cleared by writing a one. In case of multiple enors, only the first one is logged. If multiple errors are detected in the same cycle, the follow-ing priority is used:
Priority Error
1 Grant Parity Error 1 Oynabus Parity Error 3 Grant Time Out 4 Internal Errors
NOTE: If multiple internal errors oa:lD' within the same cycle, ME is not set to one, but multiple error bits may be set in the DynaData register (See section 4.S.4.2 on page 64).
DPE: Oynabus Parity Error. This bit is set to one when a parity error is de-tected on Oynabus for either a Oata or a Header cycle. When a Oynabus parity error is detected, the faulting cycle is latched in the OynaData register and the parity sig-nals are latched in the ErrLog field. This bit is cleared by writing a one.
GPE: Grant Parity Error. This bit is set to one when a parity error is detect-ed on the arbitration signals. When such an error is detected, the value of the arbi-tration signals is latched in the ErrLog field. This bit is cleared by writing a one . . GTO: Grant Time-Out. This bit is set to one when the time-out counter for.
a Oynabus grant oveif1ows. This bit'is cleared by writing a one .
. CDE: Client Device Errors. This field is used to report internal errors. The nature of the error is logged in the OynaData register. This field has the following structure: