There are two Counter-Tuners in each Bus Watcher.
The first Counter-lamer is used as profile timer. It supports a free running mode called the user tilMr 1fIDM. This timer generates interrupts at level 14 (lNTSJD-o)
to the auached processor. Software should use only the proftle timer in the Bus Watcher auached to Dynabus II 0, to allow proper operation when a single Dynabus is enabled.
The second Counter-Timer is used as a Unix tick timer. It generates interrupts at level 10 (lNTSID-l) to the attached processor. This Counter-Tuner does not super
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pan the user timer mode. There should be only one such timer used in a Sun-4D systems system. As for the profile timer. the tick timer should be attached to Dyna-bus 1# O. The processor whose tick timer is enabled will receive all the corresponding interrupts. and is in charge of re-dispatching them.
The Counter-Timers are cleared at reset.
Counter-Timers Structure
Both Counter-Timers have the same structure. They consist of a 32-bit Counter reg-ister, a 32-bit Limit register and a 32-bit Non-Destructive Limit register. The profile timer also includes a 32-bit Control register to enable the user timer mode and a 64-bit User Timer register. The structure of the registers is described below.
The Counter. Limit. Non-Destructive Limit and Control registers are accessed as words. The User Timer register is accessed as a word or double-word.
The Counter register has the following structure:
Value Rsvd
31 30 10 9 0
The various bit fields have the fcUowing meaning:
Rsvd: Reserved: This field is ignored on a write and read as zero Value: The Counter value is incremented every microsecond. When the counter value becomes equal to the Limit value. the bit L is set to one, the Counter value is·reset to one (and keeps being incremented) and an intemJpt is issued to the . attached processor if L was· not already set. It must be noted that a specific bit is set . in the Interrupt Table when a Counter-Timer intemJpt is issued. The profile timer
uses the INTSID value OxOO and the tick timer the INTSID value OxOl.
L: Limit bit This bit is set to one when the Counter value is equal to the Limit value. This bit is cleared when the Umit register is read.
The Counter register is readable and writable. When it is read. the Counter value is frozen until the read completes but no increment is lost.
The Limit register bas the following structure:
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LI
Value RsvdI
31 30 10 9 0
The various bit fields have the following meaning:
Rsvd: Reserved. This field is ignored on a write and read as zero
Value: Limit value. Setting the Umit value to zero configures the timer in a free-running mode where no interrupt is issued. Note that, when the timer is in free-running mode. the L bit is still set normally, althougb no intemJpt is issued.
L: Limit bit This bit is the same as the limit bit of the Counter register.
It is set to one when the Counter value is equal to the Limit value. It is cleared when the Limit register is read.
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The Limit relister is readable and writable. When the Limit register is read the L bit is cleared. When the Limit relister is written the Counter value is reset to one.
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The Non-Destructive Limit relister is the same physical register as the Limit regis- '''-,. ,"
ter. A read of this relister has the same effect as a read of the Limit relister. When this relister is written the Counter value is not reset to one. This pseudo-register is provided to implement alann-clock interrupts.
The following relisters are defined only for the profile timer. The profile timer may be configured in user timer mode with bit UTE of the Bus Watcher Control register (See section 4.5.5 on page 66). When the user timer mode is enabled, the Counter and Limit relisters are merged in a 64-bit counter register called the User Timer relister. This relister has the following structure:
I
LI
Value Rsvd63 62 10 9 o
31
The various bit fields have the following meaning:
Rsvd: Reserved. This field is ignored on a write and read as zero
Value: Counter value. The Counter value is incremented every microsec-ond. When it overflows. the bit L is set to one but no interrupt is generated.
L: Limit bit. This bit is set to one when the Counter value overflows. It is cleared when the relister is written.
The User Timer relister should be accessed as a double word. When it is written, the bit L is cleared .
. 'The Control relister has the follOwing structure:
Rsvd
IUCENI
1 0 The various bit fields have the following meaning:
Rsvd: Reserved. This field is ignored on a write and read as zero
UCEN: Enable user timer counting when set to one. When it is zero the User , Timer is frozen.
Prescaler Register
The Prescaler relister is used to generate a 1 MHz clock. The Prescaler relister is accessible as a half-word and is readable and writable.
The Prescaler register has the following structure:
PRZERO PRCNT
IS 8 7 o
The bit fields have the following meaning:
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