Routln. Cod. Function Telted Error Delcription Locltlon(a) Milk Plgt PlgI Comm.nta
X94C OX20
If the irpt expected in codes OX19 and OX21 was a data/status E4L2 PE103 H-070 Reg X'14' contains the results of the IN X'62'.and .OX22
irpt, an IN X'62' verifies that the irpt was the expected type Reg X'15' indicates the bits in error in regX94E OX24
data/status irpt. X'14'. The halfword located at X'5C' plus the(cont.) OX26
adr in reg X'12' contains the results of the INX'77' executed when the irpt occurred. This can be used to determine the selected adapter.
X950
Cycle-steal reg X'6F' test. This routine ensures that bits 1.4, 1.5, 1.6, and 1.7 of reg X'SE' and all bits of ~eg X'SF' can be set to ones. The value of X'OOO'F' is output to reg X'SE'. Reg X'SE' is read to verify that it contains X'OOOF'.The value of X'FFFF' is output to reg X'SF'. Reg X'SF' is read to verify that it contains X'FFFF'.
OX01
Error indication on input of cycle-steal reg X'SE'. E4E2 PP103 H-180 Bits expected to be set are 1.4, 1.5, 1.S, and1.7. Results of input should be i., reg X'14'.
Bits in error should be in reg X'15'.
OX02
Error indication upon input of cycle-steal reg X'6F'. E402 PP101 H-180 Results of the input are in Reg X'14'. All bitsare expected to be set. Bits in error should be in reg X'15'.
X952
Cycle-steal adr and outbound data transfer test. This routine tests for the proper functioning of the cycle-steal adr regs, X'SE' and X'SF' and for the transfer of data from storage to the data buffer reg X'SO'.On successive passes, cycle-steal operation is executed in diagnostic mode. Starting with a 2-byte cycle steal, each cycle steal is incremented by 2 until 25S bytes are transferred in the last pass.
On each pass, the cycle-steal operation is requested with an output to reg X'SC'; the data out adr is output to reg X'SE' and reg X'SF'. Outbound transfer is requested with OUT X'S2' and the cycle-steal is initiated by outputs to reg X'67'.
Output X'S7' is executed on each pass, once for each byte in the count in reg X'SC'.
The resulting cycle-steal adr in registers X'SE' and X'SF', when in steal mode, is 2 bytes higher than when in normal cycle-steal mode. With this in mind, the cycle cycle-steal adr is checked on each pass to be 2 bytes higher than normal, and the data in register SO is compared with data that is 2 bytes beyond that data normally expected:
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3705-80 TYPE 4 CA 1FT SYMPTOM INDEX - Cont.
Error Suspected eerd Program FEALD FETMM
Routine Code Function Tested Error Description Location(s) Mask Page Page Comments
X952 OX01 Cycle-steal adr error. E4E2 PP103 H-180 Value obtained from reg X'6F' is in reg X'14'.
(cont.) E4D2 PP101 H-180 Adr expected is in reg X'13'. Bits in error in
reg X'15'.
OX02 Cycle-steal data error. E4J2 PK102 H-160 The value obtained from reg X'6D' is in
reg X'14'. The value expected from reg X'6D' is in reg X'13'. The bits in error are in reg X'15'.
X954 Cycle-steal adr and inbound data transfer test. This routine tests for the proper functioning of the cycle-steal adr reg X'6E' and X'6F' and for the transfer of data from the buffer reg X'6D' to storage.
On successive passes, cycle-steal operations are executed. The byte count of each cycle steal is incremented by 2, from 2 to 256 bytes.
On each pass, the cycle steal operation is requested with an output to reg X'SC'; the data in adr is output to reg X'SF' and reg X'6E'. Inbound transfer is requested with IN X'62' and the cycle steal is initiated by outputs to reg X'S7'.
Reg output X'S7' is executed the number of times equal to the cycle steal count.
After each operation, the cycle-steal adr is verified to have incremented by the same value of the cycle-steal count, and the data in storage is verified to be that from the buffer reg X'SO'.
OX01 Cycle-steal adr error. E4E2 PP103 H-180 Value obtained from reg X'SF' is in reg X'14'.
E402 PP101 H-180 Adr expected is in reg X'13'. Bits in error are
in reg X'15'.
OX02 Cycle-steal data error. E4J2 PK102 H-180 Value obtained from storage is in reg X'14'.
Value expected in storage is in reg X'13'. The bits in error are in reg X'15'.
X956 Cycle-steal outbound odd-even count and adr test. This test verifies proper performance of the cycle-steal operation, whether count or storage adr is odd or even.
This test makes four passes. The first is an outbound transfer of 3 bytes from an even adr.
On the second pass, the adr is made odd.
On the third pass, the count is made even, and on the fourth pass the adr is made even.
Error Suspected Card
Routine Code Function Tested Error Description Location(s)
X956 On each pass, cycle-steal registers X'6E'and X'6F' are verified to (cont.) be incremented as expected. The anticipated data from storage is
verified to be in reg X'6D'.
OX01 The cycle-steal adr from reg X'6F' in error on a 3-byte transfer. E4D2
OX02 The cycle-steal adr from reg X'6F' in error on a 4-byte transfer. E4D2
) OX03 Data error on outbound 3-byte cycle-steal transfer. E4D2
OX04 Data error on outbound 4-byte cycle-steal transfer. E4D2
X957 Cycle utilization counter (CUC) test. This test verifies proper incrementing of the CUC from cycle-steal cycles by the adapter under test. CUC value represents a combination of cycle-steal and instruction cycles. CUC operation of the CUC for 11, 12 and 13 cycles has been verified in the CUC diagnostic routines.
OX01 CUC value is not correct after cycle-steal operation. 1AB4-T2
(
Program Mask
.
(~ ,,--)
FEALD Page
PP104
PP104
PP104
PP104
CNOO1
FETMM Page
H-170
H·170
H-170
H-170
Comments
Reg X'14' contains the data from reg X'6F'.
Reg X'15' contains the bits of reg X'14' that are in error.
Reg X'14' contains the data from reg X'6F'.
Reg X'15' contains the bits of register X'14' that are in error.
Data expected is in reg X'14'. Bits in error are in reg X'15'.
Data expected is in reg X'14'. Bits in error are in reg X'15'.
Reg X'14' = actual CUC value Reg X'15'