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HONEYWELL INFORMATION SPEC" NO" SHEET REVISION

I

SYSTEMS ITALIA SGM2 PDD 61

PREGNANA MILANESE A78139983 OF 340 AA

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IHONEYWELL INFORMATION

I

SPEC. NO. SHEET REVISIONI

I

SYSTEMS ITALIA SGM2 PDD I 62 !

PREGNANA MILANESE I A78139983 OF 340 AA

11

+---+---+---.----+---+---~+

Cachable Resources. The SGM2 system is able biprocessor environment: the system structure

in Fig. B.2.2., The communications between ,Processors and the I/O Processors are performed

bus that is the VME bus.

to work in a is i llust ra ted

the Central by the system

The Centra"l Processor architecture permits to the MPU68020 to work in cache memory and, at the same time, its main memory

can be accessed by any master of the system bus. Then, each Central Processor can access (in read and write) the main memory of the other Central Processor and any I/O Processor is able to read/write anyone of the two Main Memories. In a such system architecture each Central Processor is tightly coupled with its own Main Memory. and Cache Memory. Each cache memory is able to cache only the Lnformation stored 'into its own coupled Main Memory: so all the accesses performed by the MPU68020 out of its Main memory space (that is, accesses on the internal resources, such as Eprom, Timer, etc., or accesses on the VME bus resources) are not cached.

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IHONEYWELL INFORMATION SPEC. NO. SHEET REVISION

I

SYSTEMS ITALLb, SG~12 PDD 63

PREGNANA MILANESE A78l39983 OF 340 AA

+---+---+---+---+---+

- V~iE Monitor. To prevent the ~1PU68020 from using stale data, each cache memory is provided of a bus watching mechanism,the VME M0nitor (see Fig. B.2.2) that ensure software transparent data consistency in multimaster systems. The VME Monitor logs all VME bus write activity related only to its coupled Main Memory and i ni t ia ted by other VME bus masters. The VME bus addresses are latched and the Monitor requests a cache check cycle. The VME address is compared to those contained into the cache and if a match occurs at a valid block, that block is i nva lid a t ed •

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IHONEY~ELL INFORt1ATION SPEC. NO. SHEET. REVISIOM

I

SYSTEMS ITALIA SGM2 PDD 64

PREGNANA MILANESE A78139983 OF 340 AA

+---+---+---+---+---+

B.3 . CACHE MEMORY OPERATIONS

This Section provides a general description of the cache memory operations, as well as detailed descriptions of all cache memory cy cles·.

The bas i c concept is connected to the behaviou r of a typical program: the main characteristics are its sequentiality associated with its looping capability. These interesting program features are used by' .the cache controller in a probabilistic manner to handle the miss/hit indicator. 'A program is executed instruction after instruction and each instruction is fet<;hed and executed by a certa i nuntlmber.;,of.J)us ^'J cycles.:··s·o:.;' r«~~'tJua!l.'rf-i~et:"~ill ·'t·erm of hit/miss can be assigned to each bus cycle. In particular, the information associated with the hit/miss indicator is referred to the previous bus cycle and it is used in the current bus cycle.

So, if in a generic bus cycle the state of the indicator is miss this implies that in the previous bus cycle the searched information was not into the cache memory and, for the program characteristics above illustrated, with a very high probability also the present searched information will not be in cache. In this case a Main Memory cycle is started and contemporarily is checked the presence of the searched information in the cache: if present, the state of the indicator will be changed in hit, if absent, the state of the indicator remains miss and the read information will be also stored in cache. On the other hand, if in a generic bus cycle the indicator is hit this signifies that in the previous bus cycle the searched information was pr:ovided by the cache memory and, probably, also the present information is in cache. So, in this cycle type the cache provides the DSACKO,l signals without to know really if the searched i nf ormat i on is inca che: th is permi ts to execut e the pres ent bus cy,cle without wait-states. Then, if a real hit is found out, the cache provides the information to the MPU68020 and the hit/miss indicator is unchanged: when the information is not 'in cache, HALT and BERR signals will be asserted (the MPU68020 rerun the same cycle) and the indicator assumes the miss state. Because the indicator is put. in miss state, when the MPU68020 reruns the cycle, the Main l-temory will provide the searched information. It must be pointed' that the rerun cycle is payed only when after a series of hit cycles in cache memory occurs the miss condition. During a sequence of miss cycles ( Mai n Memory cycles ) the rerun mechanism does not work. In reality tpe previous hit/miss indicator is splitted into the following hit/miss indicators: Supervisor Program, Supervisor Data, User Program and User Data. Each indicator is used by the cache controller to menage the related current bus cycle on the base of the behaviour detected in the previous cycle.

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IHONEYWELL INFORMATION I SPEC. NO. SHEET REVISION

I

SYSTEMS ITALIA . \ SGM2 PDD 65

PREGNANA MILANESE A78139983 OF 340 ·AA

+---+---~---+---+---+---+

The above cache operations can be summarized with the control-state diagram showed in Fig. FL3.1. Each state is entered under speci·fic Conditions, performs specific cache activities, and decides which is the next state to reach. The cache memory control-state diagram is made up of 13 states: when the cache memory has nO activities running, then it is in the CACHE IDLE state. It must be pointed 'out that a cache memory cycle is constituted by some cache states. The following 9 cache cycle are illustrated in Fig.

B.3.1:

- HIT cycle,

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- RERUN cycle,

- CAtHE REPLACE cycle, U PDAl'l'£I·.INOt·CATOR"

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- WRITE THROUGHT cycle, - CACHE NOP cycle,

- CACHE WAIT cycle'-- MONITOR CHECK cycle, - CACHE FLUSH cycle.

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The Table B.3.1 summarizes in detail the conditions and the ope'rations relative to each cache memory cycles.

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HONEYWELL LNFORMATION SPEC. NO. SHEET REVISION

SYSTEMS ITALIA SGM2 PDD 66

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Im Dokument PREPARED BY (Seite 62-67)