VHf BliS
B. S.S CACHE HIT/MISS DETECTION
B.5.7 CACHE DATA MEMORY
+---+---+---+---+---+
HONEYWELL INFORMATION SPEC. NO. SHEET REVISION
SYSTEMS ITALIA SGM2 PriD 114
PREGNANA MILANESE A78139983 OF 340 AA
+---+---+---+---+---+
B.5.7 CACHE DATA MEMORY
The Cache Data Memory contains a 4K by 32 bit (16 Kbytes) static RAM plus a byte level parity for store data and program information:
this memory is accessed only for MPU68020 cycles, differently by the CAM and Block Valid-Bit memories.
The "cache data block" organization and structure is illustrated in Fig. B.S. 7 • 1.
I(---~---~---~ data block --->1 bit
31 24 23
I .
16 15I
08 07
bit 00
<--byte3-->I(--byte2-->I<--bytel-->I(-~byteO--> (-- parity -->1 check bits (--- Data Bus --->1
CDAT3l CDATOO
Fig. B.5.7.l Data Block Structure
The Cache Data Memory is physically implemented by twelve high speed (25 ns access time) Static RAM 4Kx4 of which eight store data and program information and the other four are used as SRAM 4Kxl for the parity bit storing: the organization of the Cache Data Memory is shown in Fig. B.5.7.2. This module also includes two other hardware blocks: the "Data Transceivers" and the "Parity Generator a,nd Checking Logic".
The Cache Data Memory is accessed in READ, during the Hit and Rerun cycles, always at Long Word (32 bits) level: the data provides by the Data SRAM is delivered to the MPU68020 through the Data Transceivers and contemporarily are received by the Parity Checking Logic with the four Parity Check signals provided by the Check SRAM.
The Parity Checking Logic produces four combinatory parity error signals (CDCERx+OO) active at level ONE: the CDCERx signals are strobed only in the Hit cycles and even if only one is active, the MPU68020 HALT signal is asserted because an incorrect data was
latched by the microprocessor.
c;
c
C·\
,/ I+---+---+---+---+---~
HONEYWELL INFORMATION SPEC. NO. SH~ET REVISION:
SYSTEMS ITALIA SGM2 PDD 116 \'
PREGNANA HILANESE A78l39983 OF 340 AA
+---+---+---+---+---.
The Ca'che Data Memory is accessed in WRITE in the Cache Replace and Write Through cycles. During the Cache Replace cycle, that is a Read cycle 'for the ~1PU68020, the Long Word (32 bi ts) provided by the coupled Main Memory is also stored into the cache Data SRAM with the four odd parity check bits provided by the Parity Generator Logic and stored into the cache Check SRAM. During the Write Through cycle with the hit condition present the data provided by the MPU68020 update the coupled Main Memory contents and also the cache memory contents: this updating can occur at byte, word, three bytes, and long word level and the parity check bits are generated in correlated manner.
,
The 'Cache Data Memory is addressed by twelve addresses: the ni ne leas t ··:6i4;rni~i,.oa.nt-.a re ·the·(JPADOOS'-'l'A~'2 -'8'dd'!'esses . prov id ed direct ly by the MPU68020 (only a DRIVER circuit is present). The three most significant come from the High Address Encoding Logic (see Section B.5.4) that produces a coding (on three bits) of the actual hit sector number.
c
\ ",,-"
o
'",~ ....
+---+'\---+---+ ---- ----+---
--+HONEYWELL I~PORMATION \ SPEC. NO. SHEET REVISION\
SYSTEMS ITALIA SGM2 POD 1 1 7 !
PREGNANA MILANESE A78139983 OF 340 AA j
+---+---+---+---+---~
B.5.8 VME BUS MONITOR
When a VME Bus master executes a write cycle towards the coupled Main Memory, the VME Monitor latches in the dual buffer FIFO the associated address and requests a Monitor Check cycle. I f cached (valid), that entry is invalidated to eliminate stale data in the cache. Only very fast VME Bus write activity (cycle time faster than 180 nanoseconds) may overrun the Monitor dual buffer FIFO: actually any VME Bus cycle is forecasted longer than any MPU68020 cycle. In ,any case, the overrun condition will clear the cache (a Cache Flush
cycle is executed) and assert the CDMOWF-OO signal (Monitor Overflow') that will produce a software handled level 7 MPU68020
interru.J;:.!:.., """,',' ,,',,'.' .,.('~ .. ".;. ,,' " d , : __ ',.,
The VME Bus Monitor (refer to Fig. B.5.8.1) consists of the VME Bus signal receiver circuitry, the dual buffer FIFO used to latch the VME Bus address and the Monitor Timing and Control Logic.
The VME Bus addresses (VADD31-VADD02) are latched at the beginning of any VME Bus' cycle by the' rising edge of the CADSTB+OO signal and so the CADD31-CADD02 addresses do not change, until the
next VME Bus cycle-; this 'latching operation is performed on any type of VME Bus Read/Write cycle. ThEi" CADDli-CADD02 addresses go directly to the first FIFO buffer; instead the group CADD25-CADD12 can be modified (see Table B.S.8.1) depending on the VME Bus Master type and according to the VME Bus maps (see CPO POD). The VME Bus Master type is detected coding the VME Bus address modifiers (CADMD5 and CADMD4 signals; see also Table B.5.8.l).
Table B.S.8.1 Handling of the CADD25-CA0012 Addresses
VME MASTER CADM25 CADM19 CADM15 CAOMD5 CADMD4 TYPE' CADM20 CADM16 CADM12
--- --- --- --- ---
---SHORT
1 0 ( 16 ) 0 0 0
STANDARD CADD19 CADDIS
1 1 (24 ) 0 CADD16 CADD12
.
EXTENDED CADD25 CADD19 CADDl5
0 0 (32 ) CADD20 CADD16 CADD12
o
~.,.
0
+---~~---+---+---+---+---+
HONEYWELL INFORMATION SPEC. NO. SHEET REVISION
SYSTEMS ITALIA SGM2 PDD 118
Monitor 74FI09
h4F04J
Control Logic Fig. B.S.8.1 VME Bus Monitor Block Diagram
/ I
c
c
+---~---+---+---+---+---~
HONEYWELL INFORMATION SPEC. NO. SHEET !REVISION\
SYSTEMS ITI\L IA SGM2 POD 119
I '
PREGNANA ~HLANESE A78139983 OF 340 AA
I
+---+---~---+---+---+---+
I t must be pointed that is requested to load in the VME· FIFO only the VME addre5ses. corresponding to the Sector Address Field (stored into the CAM memory; CADM25-CADM12,CADD11) a nd the Block Address Field (CADDIO-CADD02) to detect the Block Valid-Bit.
Actually, the VADD27 and VADD26 addresses are received but not used in anywhere.
A VME Bus master performs a "Cache VME Valid Main Memory Access"
(that is, the CVMMIN-OO s ig nal is asse rted) under the cond i t i ons described in the Table B.5.8.2. Only the accesses toward the coupled Main Memory are take into account because the other Main Memory
contents are not cachable.
'.
Table B.5.8.2 Cache VME Valid Main Memory Access
C C C C C C C C V C C A A A A A A A A P A V D D D D D D D D N C M M M M M M M M M U A M D D 3 2 2 2 1 1 M C I 5 4 I 7 3 0 5 2 0 T N
+ +
---- ---- --- --- --- ---
---x x x x x x x 1
0001 0
V SHORT 1 O' NA NA 1 0
M 0010 1
E
0001 0
M STANDARD 1 1 NA NA 1 0
A 0010 I
-S
T 0001 0
E EXTENDED 0 0 NA NA 1 0
R 0010
-1-x --~ don't care NA
-->
Not ApplicableI f the CVMMIN-OO signal is asserted and the VME cycle ia a WRITE cycle (CLWRIT-OO signal asserted; this signal is latched at each VME cycle by a strobe that is the ored VME Data Strobes) the CYCLOK+OO signal is asserted and only in this case when the coupled Main Memory drives the VDTACK-OO signal the CLOAD1+00 clock is activated (see Table B.5.8.3). This means that, in normal mode, if the coupled Main Memory detects an error and drives the VBUERR-OO' signal, the.
CLOADl+00 clock is not asserted and no real VME Monitor activities are performed.
+---+---+---+---+--~---+ VBOERR-OO signal for time-out expiration.
c
+---+---+---+---+---+
HONEYWELL INFORMATION SPEC. NO. SHEET REVISION
SYSTEMS ITALIA SGM2 POD 121
PREGNANA MILANESE A78139983 OF 340 AA
+---+---+---+---~---+
The Monitor dual buffer FIFO operations are:
- storing the V~tEaddress in the first FIFO buffer:
- shift the first FIFO buffer contents into the second FIFO buff er;
- set the VME Monitor request;
- set (if the case) the VME Monitor Overflow condition.
The above operation are handled by three flip-flops: fifo FULL, MONitor REQuest, and MONitor OVerFlow (see Fig. 8.5.8.1). The operati'on starting comes on the rising edge of the CLOADl+OO signal as shown in Fig. 8.5.8.2.
CLOADl+OO
... I
v
-L
.,...-_ _ ...;;.;N_/FULL
=
0 \_Y::..-_ _-.-\ 1
v v
Set MON OVF f lip- flop
. Store VME Add.
• Set fifo FULL
I I
v v
Cache Flush Cycle Requested
~ ____ ~N_/MONREQ
=
1 \~Y ________ ~\ _ _ _ _ _ 1
v
WaitMON REQ
=
0(Monitor Check Cycle pend i ng 0 r inS e rv • )
<--- I
v
• Shift VME Address
• Set MON REQ
• Reset fifo FULL
I
Monitor Check Cycle v RequestedFig~ B.5.8.2 Monitor Dual Buffer FIFO Activities
c
+---,---+---+---+---+---+
HONEYWELL INFORMATION SPEC. N0'1 SHEET !REVISION
SYSTEMS ITALIA SGM2 POD 122
PREGNANA MILANESE A78139983