CACHE REPLACE CYCLE

HONEYWELL INFORMATION SPEC. NO. SHEET REVISION

SYSTEt-tS ITALIA SGM2 POD 73

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B.3.3 CACHE REPLACE CYCLE

The CACHE REPLACE cycle is made up of CACHE IDLE, START Main ~1emory, CACHE BUSY, Fig. B. 3 • 3 • 1) •

the follow i ng s tat es : a nd CACHE REPLACE (see

This cycle begins from the CACHE IDLE state and the START Main Memory state is reached under the following conditions:

51.

the MPU68020 has started an external cycle (that is, LAS signal is asserted) i

52". the external cycle is performed towards the Main Memory I,,' ',,;':"'SpaiCe' ','C'h'a't.,'< 'l'ftea'ffS i"t.OWa't'OS·' 'tne"'" cQup'lea-"'Ma 1 Ti"'Memory ot" tha t

one of the other CP: in any case only user program/data or supervisor program/data are taken into account;

s3. the cache is active,

and when almost one of the following events is verified:

s4a. RMC signal asserted (that is, the MPU68020 is executing a TAS or CAS instruction);

s4b. the previous hit/miss indicator is in the MISS condition.

In the START Main Memory state the cache enables the starting of the coupled Main Memory without to know which one of the two Main Memories will be accessed in this cycle. The physical address provided by the MMU decides which memory must handle the current cycle. If the memory of the other CP must execute the present cycle a VME bus cycle must be requested by the coupled CP: in this case the started coupled memory will close the cycle without provide the data.

It must be emphasized that the cache board controls the "Start Main Memory Mechanism" only when it is active; on the other hand, when the cache is present but "no active", the start of the 'coupled Main Memory is performed by the CP board and pratically follows the LAS signal assertion.

The CACHE -BUSY state is reached when the' followi ng events are veri'fied:

bl. the PAS signal is asserted;

b2. the MPU68020 has requested a cycle towa rds 'the coupled Main 1I1emory (the signal DC64P-OO is active).

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HONEYWELL INFORMATION SPEC. NO. SHEET REVISION1

SYSTEMS ITALIA SG~12 PDD 74

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HONEYWELL INFOR~1ATION

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I n the CACHE depi cts only an

BUSY state no specific action is performed: it intermediate state between the START ~1ain Memory

following four states: CACHE REPLACE, UPDATE THROUGHT, and CACHE NOP.

s tat e and ,t h e INDICATOR, \-lRITE

At' this point the passing to the CACHE REPLACE state is determined by the following conditions:

pI. the cycle started by the ~1PU68020 is a READ cycle i

p2. the RMC s ig na 1 is not asserted;

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the selected previous hit/miss i ndi cator is in the MISS state;

p4 : the sector miss or the block miss condi tion is asserted.

When a sector miss occours the following activities are pe rf ormed :

sml. the FIFO Replacement Algorithm (see Section B.2) is pratically implemented by a shift register used to point the sector resources to be updated: so, first of all, the shift register i"s clocked one time, that is, a shift right operation is performed; at this point, the output at

"level one" indicates which sector resources must be replaced;

sm2. the CAM sector register pointed by the shift register "is loaded with the current Sector Base Address, that is, with the physical address 11 through 25; at the same time the validation of the relative Sector Valid Bit is performed;

sm3. the section of the Block Valid-Bit Memory actually pointed by the sh i ft reg ister is completely invalidate because now it is referred to a new Main Memory sector;

sm4. the block valid bit (addressed by the current block address field) of the Block Valid-Bit Memory actually pointed by the shift register is set (to logic ONE) if the Mai n Memory cycle is correct ly , termi na ted (BERR s ig na I not asserted): otherwise it remains in the not valid status

(logic ZERO);

· ... ~~~~~".'"~-~"~~'~-~"~'.'-""""'f'",,-.,",,~:~..:;~~~~-:.:;.";:;::";;;::.::. -.:::::+:::.:- - - + - - - -+

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smS. the Cache Data Hemory block (four bytes) addressed by the current block address field of the "actual pointed slot"

is replaced with the long word (with the relative four computed check bits) provided by the Main Memory. The Cache Data Memory slot is pointed by a combinatory network that encodes the eight mat.choutputs of the sector comparators into three signals that represents the three most significant Cache Data Memory addresses. The Sector Comparators and the Slot Encoding Logic are physically connected after thee Sector Registers (CAM), are always active, and always work on the basis of the Sector Registers contents and of the actual sector address field value.

If ~n!ly'·a~··)'bTo~·"mtss·'<occurs, t·ha·t"1.'s,the current· sector field matches with one 'of the eigth sector addresses stored in the CAM,

the following operations are executed:

bml. stori ng of the sector number that has provided the sector hit condition in the Hit Sector Number Register which will point the sector resources to replace;

bm2. the block valid bit (addressed by the current block address field) of the Block Valid-Bit Hemory actually pointed by the Hit Sector Number Register is set (to logic ONE) if the Main Memory cycle is correctly terminated (BERR signal not asserted): otherwise it remains in the not valid status (logic ZERO);

bm3. same operations described in point smS.

When the "end cycle" cond it i on is det ected (LAS s ig na 1 negated by the MPU68020) the IDLE state is s t i l l reached.

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IHONEYWELL INFORMATION SPEC. NO. SHEET I~EVISION

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SYSTEMS ITALIA SGt-12 POD 77

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B.3.4 UPDATE INDICATOR CYCLE

The UPDATE INDICATOR cycle is composed by the following states:

CACHE'IDLE, START Main Memory, CACHE BUSY, and UPDATE INDICATOR (see Fig. B,.3.4.1).

The START Main Memory and CACHE BUSY states are reached under the same conditions and perform the same operations explained for the CACHE REPLACE cycle (see Section B.3.3) •

The UPDATE INDICATOR state is reached when:

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ul,~ the cycle star:ted" ,l?y,.the",MPIJ6B,O'.2D,,~i.,s,.a.)?E.!\D,.;.c~,cl,e;

Li'2'.""th-e"'RMC's'ig'ria1. 'is not asserted;

u3. the selected previous hit/miss indicator is in the MISS state;

u4. the total hit condition (sector hit and block hit) is asserted.

In this state the selected previous hit/m.iss indicator is positioned in the HIT status: the sought data is s t i l l delivered to the MPU68020 by the Main Memory.

At this point, the "end cycle" condition is waited (LAS signal negated by the MPU68020) and then the IDLE state is reached.

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HONEYWELL INFORMATION SPEC. NO. SHEET REVISIONi

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B.3.5 WRITE THROUGH CYCLE

The WRITE THROUGH cycle is made up of CACHE· IDLE, START Main Memory, CACHE BUSY, Fig. B. 3 .5 • 1) •

the following states:

a nd WRITE 'rHROUGH (see

The START Main Memory and CACHE BUSY states are reached unde,r the same conditions and perfonn the same operations explained in the CACHE REPLACE cycle (see Section B.3.3) •

The WRITE THROUGH state is reached when the following events are

.

veri f i edF

wI. the cycle started by the MPU68020 is a WRITE cycle~

w2. the total hit condition (sector hit and block hit) is asserted.

In this state, the current pointed block is updated with the data provided by the MPU68020. The block and related check bits updating can be done at one or two or three or four bytes level according to the status ·of the PADDOO, PADDOl, SIZEO, and SIZEl signals driven by the MPU68020.

The IDLE state is reached when the "end cycle" condition (LAS signal negated by the MPU68020) is detected.

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IHONEYWELL INFORMATION SPEC. NO. SHEET REVISION

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SYSTEMS ITALIA SGM2 POD 80

Write Through Cycle Diagram

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B.3.6 CACHE NOP CYCLE

The CACHE NOP cycle is made up of the following states: CACHE IDLE, START Ma in Memory, CACHE BUSY, a nd CACHE. NOP (see Fig.

B.3.6.1).

The START Main Memory and CACHE BUSY states are reached under the same conditions and perform the same operations explained for the CACHE REPLACE cycle (see Section B.3.3).

The CACHE NOP state is reached when the following conditions.

occur: I

nl. the cycle started by the MPU68020 is a.WRITE cycle;

n2. the sector miss or the block miss condition is asserted.

In the CACHE NOp· state no action is performed because the MPU68020 is updating an infprmation "not present in cache.

Also in .this cycle,· the "end cycle" condition is waited (LAS signal negated by the MPU68020r and then the IDLE state is reached.

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HONEYW8LL INFORMATION SPEC. NO. SHEET REVISION

SYSTEMS ITAL IA SGM2 POD 82

Im Dokument PREPARED BY (Seite 74-83)