>e (NSSC-SI)

(1)

NASA STANDARD

1

SPACECRAFT COMPUTER (NSSC-SI)

> e

¹

4

4 PRINCIPLES

OF

OPERATION

2

'6

I

U n c l A S

0 2 5 2 7 6 3

(2)

DESCRIPTION ^{Y A I C} n r r $ $ u * L U

'-

;I I ;" 1

^ENGRG^NOTICE ^LTR Initial Release

-

^{a -} , 2 / 1 5 / 77

Errata Sheets 5/15/79

The attached pages are replacements or additions to the

NSSC-I1 Principles of Operation.

NAS8-32808

CONTR NO.

PREPARATION

I

I NTE R N AT1 ON A L BUS1 NESS MACH I N ES CORP.

FEDERAL SYSTEMS DIVISION

GAITHERSBURG, MARYLAND

NASA Standard Spacecraft

Computer I1 (NSSC-11) Principles of Operation

SIZE CODE IDENT NO, DWG NO.

7935402

SCALE WT SHEET

(3)

i

f d S e c t i o n

i

V I 1 1

4 .!

TABLE Paragraph

7.4.4

7.4.5 7.4.6 7.4.6.1 8.1 8.1.1 8.1.2 8.2 8.2.1 8.2.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.5.8 8.5.9 8.6 9.1 9.1.1 9.1.2 9.1.3 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.10 9.3.11 3.3.12 9.3.13 9.3.14 9.3.15

OF CONTENTS (CONTINUED) T i t l e

Branch on Index High

Branch on Index Low o r Equal Execute

Execute Exceptions STATUS SWITCHING Program S t a t e s

.

Problem S t a t e Wait S t a t e P r o t e c t i o n

Area I d e n t i f i c a t i o n P r o t e c t i o n Action Program S t a t u s Word I n s t r u c t i o n Format I n s t r u c t i o n s

Load PSW

S e t Program Mask S e t System Nask S u p e r v i s o r C a l l S e t S t o r a g e Key Test and S e t

S t a r t I n p u t Output T i m e r Read and S e t Diagnose

Status-Switching Exceptions INTERRUPTIONS

I n t e r r u p t i o n Action I n s t r u c t i o n Execution Source I d e n t i f i c a t i o n Location Determination Input/Output I n t e r r u p t i o n Program I n t e r r u p t i o n Operation Exception

Privileged-Operaticri Exception Execute Exception

P r o t e c t i o n Exception Addressing Exception

S p e c i f i c a t i o n Exception Data Exception

Main Storage

Ad

dreea ing

Information Processing Storage Protection CPU

Central Proceeeing Unit Function8 General Regietare

Arithmetic and Logical Unit Fixed Point Arithmetic Decimal Numbere

Logical Operations Program Execution Inatruction Format Addrees Generation Base Addrese

(B)

Index (X)

Diaplacament (D)

Sequential Inrtruction Execution Branching

Program Statue Word Interruption

External Interrupts Program Interrupts

Input /Ou tput fnterrup t ion Machlne States

Running or Waiting State Maeked or Interruptible State

Supervisor or Problem State Direct 1/0

Buffered 1/0 Syrtm I/O

Pane

i 1

1

1 2 2 2 2 2

6

6 \

7

7 7 8

9 10 10 .lo

12 12 12 13

14

14 15 16

17

19 19 19 19

19

19 20

20

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Section

Iv

PrrasraDb 3.7.3

3.7.4 307.5 3.7.6 3.7.7 3 * 8 3.9 3.9.1 3.9.2

4.1

4.2 4.3

4 a 4

4.5 4.5*1 4.5.2 4.5.3 4.5.4 4.5.5 465.6 4.5.7 405.8 4.5.9 4,SalO 4.5.11 404.12 4.5.13 4.5.14 4.5.15 4o5.16 405.17 4.5.16 4.5.19 4.5.20 405.21 405.22 4.5.23 4.5.24 4.5.25 4.5.26

4.5027 4.6

TABLE OF

Memory Accere

(DMA) Input /h tpu t @era

tione

Buffered 1/0 Statue Word Service Interrupt

T8E 1/0 Devices

Teat Support Equipment Function

Code

Syrtem Reset

-

Soft stop

FfXED-POINT ARITHMETIC Data Format

Number

Repreeantation Condition Code

Inotruction Format Inrtructionr ^, Load

Lord Halfword Lord and Tart Load Complament Load Poritive Load Negative

Load

Multiple Add

Add Halfword

Add

Logical

Subtract

Subtract Halfword Subtract Logical Compare

Compare Halfword Multiply Halfword Divide

Convart to Binary Oonvert to Decimal Store

Store Halfword Store Multiple Shift Left Single Shift Right Single Shift Left Double Shift Right Double

Flxad-Point Arithmetic Exceptions Multiply

iii

Pam

20

20 22 22 23 28

28

28 30 31 31 32 33 . 33 34 36

36

37 37 38 38 39 39

40

41 42 42 43 44 45 45

46

47

48

49 49 50 50 51 52 53 53 54

1

(6)

0 ^{TABLE OF}

^CONTENTS(CONTIXUED) 9 w i 0 n

V

Ew!a?mh

^Title

DECIMAL

ARITHMETIC

Sal Data Format

Salal Packad Decimal Number

Sa1.2 Zoned Decimal Number

Sa2 Nunbar Representation

5.3 Inatructione

5a3.1 Pack

5.3.2 Unpack

5a3.3

M o w

with Offeat V I

6.1

6ala1 6ala2 6.2 6a3 6a4 6.4a1 6.4a2 6a4a3 6.4.4 6,4,6 6a4aS 6a4.7 6a4.0 6a4.9 6a4a10 6.4.11 6.4.12 6.4.13 6.4a14 6a4a15 ^' 6a4.16 6a4.17 6.5 V I 1

7 . 1 7 a l a l 7a2

7

a 3 7a4 7a4a1 744a2 7.4.3

LOGICAL OPERATION Data Format

Fixed-Length Logical Infornution Variable-Length Logical Information Condition Coda

Iartruction Format Inrtructlonr

Mova

Move Numrricr Move Zonea Compara Logical

And

or

Exclurive Or

T u t

Under Mark Inrart Choractar Store Character Lord Addreir Trarlate

Tranrlate and Teot Shift Left Single

Shift

Right Single Shift Left Double Shift Right Double

Logical Operation Exceptionr BRANCHING

Normal Sequential Oparation . Saquential Operation Excoptionr Dacielon-Making

Inrtruction Fornrcrtr Branching Inrtructiona Branch on Condition Branch and Link Branch

on

Count

56 56 56 56 56 5T 57 58 59 60 60 60

61

62

62 64 65

66 C6 67 68 69 70 71

?2 72 72 73 74 75

75

76 76 77 79 79 80 02 02 84

a4

87 07

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TABLE OF CONTENTS (CONTINUED) Paranra~b

7.4.4

7.4.5

7.4.6 7.4.6.1 8.1 8.1.1 8.1.2 8.2 8.2.1 8.2.2 8.4

8.3 8.5

8mSel 8.5.2

8.5.3

8.5.4 8.9.5 8.5.6 8.567 8.5.8 8.569 8.6 9.1 9.1.1 9.1.2

9.1.3 9.2

9.3 9.3.1 9.3.2 9.3.3 9.3A 9.3.5 ,9s3m6

9.3.') 9.3.8 9.3.9 9.3.10 9.3.11

Title

-

Branch on Index

High

Branch on Index Low or Equal Execute

Execute Exception6 STATUS SWITCHING Program Statee Problem State Wait

Stat

e Protection

k o a

Identification Protection Action Program

Status

Word Iartruction Format Ine

truct

ionr

Load PSW

Sot Program Mark Sot Syrtem

Mark

Suporvieor Call

Sat

Storage

Key

Teet and Set

Start Input

Output

Tlmer Read and Set Diagnose

stAtU6-sWitChing Exceptions INTERKUPTXONS

Interruption Action Itutruction Execution Source Identification

Location Detarmlaation

Iapu

t

/&A

tpu t

.Interruption

Program

Interruption Oporation Exception

Privileged-Operation Excoption Execute Exception

Ptotoction Exception Mdreering Exception Specification Exception Data Exception

Fixed-Pointdverflaw Exception Fixed-Point-Divide Exception Buf farad

f / O

Exception

Supervieor-Call Interruption

t

Pane 88 89 89 91 92 92 92 93 94 94 94 94 96 97 98 99 99 99 100 IGO 101 103 104 104 106 106 106 107

108

108 109 110 110 110 110 110 111 111 111 111 112 112

&._ _.-__. . .. ..

_.

^._.__ ...

.._-_

^.-..^-..- ^.-,.*-.-.-..(I -,.

..*.

^...

^. ^.. ^.

^.^<^e^-^.^-

(8)

TABLE

OF

CONTENT8 (CONTINUED)

.:% : *

X

9a4 Erternrl Interruption

9a4.l Tfmor

9.4.2

Intarrupt Key

94.3 Intrrval

_Tlmer

**9*5 Machine-Chack Interruption 10.1**

loa2 loa3 10.4 10.5 10.5.1 10.5.2 10.5.3 1OaSa4 10.5as 10a5o6 10.5a7 1OeSa8 1OaSa9 10,s

^a

SHORT PRECISION OPTION Data Format

Number Representation Condition Code

Inn truc tion Format Inrtructioni

ADD Halfword ADD Short

Branch Unconditional Compare Halfword Compare ~ogical Short Compare Short

Divide Short

Load Mdrers Short Load Complement Short

Load Full to Short Regintar Load Halfword

Load Negativr Short Load Poiitive Short Load Short

^'

Load and Teat

Load and Test Short Mu1 tiply Halfword Multiply Short

Normallee AND

Short OR Short

.

Shift Left Arithmatic Short Shift Left Logical Short Shift Right Arithmetic Short Shift Right Logical Short Subtract Halfword

Subtract Short Tor

t

Bi tr

Exclurive OR Short

Short Precirion Exceptionr

112 113 113 113 114 115 115 116 116 117 119

121

121 122 123 124 125 126 127 127 128 129 129 130 131 131 132 133 133

134

135

136

137

138

139

140

141

142

143

144

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section

- .

^PrragrrPh

-

XI

- *

DOUBLE

PRECISION

FIXED-POINT

AMTIPIETIC OPTION

Data Format

Nunbar Rrprarantrtlon Condition Code

Inrtruction Forput Inrtructionr Lord Double

Load Complement Double

Add

Double

Subtract Doublr Comprrr Doublr Store Doublr

Double Prrcirlon Fixed-Point Arithmetic Excrptionr

FLOATING-POINT ARITIWTIC Data Formrt

Numbor Rrprrrrntrtlon Normlitrtion

Condition Coda Inetructlon

Format

Inrtructlonr Lord

Lord

and Tart Load Complrmrnt Lord Poritlvr Load Negatlvr

Add

N o m l i t r d

Add

Unnonnrlitrd

Subtract Normalired Subtract Unnormlirad Comprrr

U l v a M v i d r Storr

Florting-Point Arithmatic Excop tionr

Mu1

tlply

146

146

146 147 148

149

149 150 150 151 152 15

3

153

155

156 157

u7

1%

159

160 16

Z

162 162 162 163 164 165 166 166

167

168

169 171

171

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PREFACE

i

Thio document

is

t h e Machine Referance Manual f o r t h e NSSC-11.

a d e o c r i p t i o n of t h e ryetem o t r u c t u r e , t h e a r i t h m e t i c , l o g i c a l , branching, s t a t u s a s i t c h i n g , f / O o p e r a t i o n o , and t h e i n t e r r u p t and timer syrtcunr.

It p r o v i d e s

The NSSC-11 i o a 1 6 - b i t , f i x e d p o i n t , microprogram c o n t r o l l e d , g e n e r a l pur- p o r e computer.

The NSSC-I1 a r c h i t e c t u r e i s t h e rame as t h e IBM System/360 a r c h i t e c t u r e . The b a s i c NSSC-I1 s u p p o r t s 83 of t h e 87 i n s t r u c t i o n s i n t h e IBM System/360 Standard I n s t r u c t i o n S e t ; t h e b a s i c NSSC-I1 a l s o s u p p o r t s t h r e e unique i n s t r u c t i o n r which c o n t r o l t h e t i m e r s , I / O , and s t o r a g e p r o t e c t i o n . The f i r s t n i n e s e c t i o n s of t h i s document delrcribe t h e b a s i c NSSC-11.

A

s h o r t p r e c i s i o n o p t i o n l e a v a i l a b l e f o r t h e NSSC-11.

sirto

of 53 a d d i t i o n a l f n e t r u c t i o n s which d e a l p r i m a r i l y w i t h 1 6 - b i t

operands. T h e m i n e t r u c t i o n r g e n e r a l l y e x e c u t e f a e t e r t h a n t h e i r c o u n t e r - , p a r t 6 i n t h e b a e i c NSSC-I1 i n e t r u c t i o n set, which o p e r a t e on 32-bit operands.

An a d d i t i o n a l i n s t r u c t i o n format is i n c l u d e d i n t h i r o p t i o n which i n c r e a s e s e x e c u t i o n rpeed and r e d u c e s main s t o r a g e r e q u i r m o n t s . The s h o r t p r a c i o i o n o p t i o n

is

d e s c r i b e d

in

S e c t i o n X,

This o p t i o n con-

\

A double p r e c i r i o n f i x e d p o i n t o p t i o n

is also

a v a i l a b l e f o r t h e NSSC-If.

This o p t i o n c o n r l o t e of 10 a d d i t i o n a l i n a t r u c t i o n s which o p e r a t e w i t h 64-bit f i x e d p o i n t operands. This o p t i o n is d e r c r i b e d i n Section X I . A f l o a t i n g p o i n t o p t i o n is a l s o a v a i l a b l e f o r t h e NSSC-11,

cansirtr

of 22 a d d i t i o n a l i n r t r u c t i o n s which are ueed t o perform c a l c u l a - tione on o p r r a n d r w i t h ^awide range of magnitude and y i e l d r e e u l t e s c a l a d t o p r e s e r v e p r e c i s i o n .

T h i s o p t i o n T h i s o p t i o n is d e s c r i b e d i n S e c t i o n X I I ,

The following _NSSC-I1 documents contain essentially the same information a e provided in t h e c o r r e r p o n d i n g Syetem/360 d o c u m e n t a t i m r e f e r e n c e d herein:

NSSC-I1 h e e m b l e r Language, IBM Number 7935401 NSSC-I1 Linkage E d i t o r , BIM Number 7935413

v i i i

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SECTION

I

NSSC-I1 ARCHITECTURE 1.1 NSSC-11 INSTRUCTION SET

_ _ _

The NSSC-I1 is compatible with the IBM System/360 Problem State Standard Instruction Set.

Instruction Set will execute properly without change on the NSSC-XI.

Problem programs written for the S/360 Standard

There are171valid NSSC-I1 instructions. Eighty-three of them are from the 87-member S/360 Standard Instruction Set. Omitted from the NSSC-I1 set are HZ09 SIO, TCH, and TfO.

Three additional iaotructione, also described below, ars:

Mnemonic

OP

Code Format Timer Read and Set

TMRS A4 RS

Start I/O

Sf0 As Rs

Set Storage Key SSK

08 RR

Note that although mnemonic

SI0

i r ured for Start

I/O,

and

is

the only NsSc-111

f/O

inotruction, it

is

not the same inrtruction (and doer not have the eame 1

op

code) ar the

360 SIO.

dercribed below.

Op codes

A4

and

AS

are unuaed in

360.

SSK does

have

the lame

op coda

06

360

SSK, but

perfoxnu a

different function,

am

_I

1.2 EXCEPTIONS

The NSSC-I1 is

a

Supervisor State compatible with the

IBM

Syrtem/360 with the following exceptions:

1 ^a2 1

INPUT/OUTPUT

The 1/0 portion of the NSSC-I1 provides the means of communication between the system f / O and test support equipment

(TSE)

with the CPU and the main store

(MS).

parallel channel providing direct

I/O,

buffered I/O, external interrupt, and direct memory access (DMA).

patible.

instruction which controls direct I / O .

In the 16 bit NSSC-I1 the 1/0 is implemented as

a

16 bit The 16 bit channel is SP-1 hardware com- There is only one 1/0 instruction

-

the SI0 (Start 1/01

All

other 1/0 i r device controlled.

1.2.2 TIMER

The NSSC-I1 has A real time clock and an interval timer, each containing both hardware and microprogramrued elements.

instruction.

Both are accessed by using the TMRS The S/360 interval timer in memory location 80 is not supported.

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The i n t e r v a l timer (INTIMER) i s 1 6 b i t s and i s decremented e v e r y 112.64 microseconds.

i n t e r v a l timer c a u s e s a timer e x t e r n a l i n t e r r u p t (which can be masked;

see paragraph 3.6.5.1, E x t e r n a l I n t e r r u p t . )

The r e a l t i m e c l o c k (RTC) i s 3 2 b i t s and i s incremented e v e r y 112.64 microseconds. It h a s a maximum of 5 d a y s , 14 h o u r s , 23 m i n u t e s , and 5.116 seconds. I t c a u s e s no i n t e r r u p t on overflow.

I t h a s a maximum of 7 . 3 8 seconds. Underflow of t h e

1.2.3 . STORAGE PROTECT

The s i z e of t h e s t o r a g e p r o t e c t b l o c k s i n t h e NSSC-I1 i s 1 0 2 4 b y t e s ( 5 1 2 halfwords) and t h e operand of t h e SSK ( S e t S t o r a g e Key) i n s t r u c - t i o n s u p p o r t s one b i t f o r CPU and Buffered I f 0 p r o t e c t i o n and a second b i t f o r DMA p r o t e c t i o n . The 4 o r 5 b i t p r o t e c t i o n key of S / 3 6 0 i s n o t supported. The i n s t r u c t i o n ISK ( I n s e r t S t o r a g e Key) does n o t e x i s t on t h e NSSC-11.

1.2.4 EXECUTION TIMES

The i n s t r u c t i o n e x e c u t i o n t i m e i s n o t t h e same f o r t h e N S C C - I 1 and any

I B M 360.

\

1.2.5 UNPREDICTABLE RESULTS

These o c c u r d u e t o a d d r e s s i n g e r r o r s , e t c . , on t h e IBH 360 series and w i l l n o t n e c e s s a r i l y b e t h e same u n p r e d i c t a b l e r e s u l t s on 'the NSSC-11.

1.2.6 ADDRESSING EXCEPTION

E x e c u t i o n of most i n s t r u c t i o n s r e s i d i n g i n t h e l a s t f u l l w o r d of memory w i l l y i e l d u n p r e d i c t a b l e r e s u l t s , u n l e s s memory s i z e i s 6 4 / K b y t e s .

1,

j

1.2.7 ADDRESSING

A l l e f f e c t i v e a d d r e s s computation i s l i m i t e d t o 20 b i t s except f o r t h e LA (Load Address) i n s t r u c t i o n , which i s 24 b i t s . E f f e c t i v e addresses l a r g e r

t h a n 6 5 , 5 3 5 w i l l be t r u n c a t e d t o 20 b i t s (modulo 1 , 0 4 8 , 5 7 5 ) and w i l l n o t cause an a d d r e s s i n g e x c e p t i o n u n l e s s t h e modolo 1 , 0 4 8 , 5 7 5 a d d r e s s exceeds t h e a v a i l a b l e main memory. I f t h e N S S C - 1 1 has 1 , 9 4 8 , 5 7 5 b y t e s of main memory, an a d d r e s s i n g e x c e p t i o n cannot occus.

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N S S C I

1 1 0 1 0 1 0 1 1 1 1 0 0 0 l 0 l t l 0 0 0 1 0 i i 0 0 0 0 1 1 0 1 1 0 0 0 0 ~ 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 ~ l 0 0 0 0 0 0

1 I

I1

i j

SECTION I1 SYSTEM STRUCTURE 2 . 1 M A I N STORAGE

The NSSC-I1 h a s a maximum c a p a c i t y of one mega--byte; however, t h e c u r r e n t c a p a c i t y i s 112K-bytes of Simplex memory o r SOK-bytes of F a u l t T o l e r a n t memory.

programmed. The system t r a n s m i t s in€ormation between main s t o r a g e and t h e CPU i n u n i t s of e i g h t b i t s , o r a m u l t i p l e of e i g h t b i t s a t a time.

Each e i g h t b i t u n i t of information i s c a l l e d a b y t e , t h e b a s i c b u i l d i n g b l o c k of a l l formats.

Bytes may b e handled s e p a r a t e l y o r grouped t o g e t h e r i n f i e l d s .

word is a group of two c o n s e c u t i v e b y t e s and i s t h e b a s i c b u i l d i n g b l o c k of i n s t r u c t i o n s .

word i s a f i e l d c o n s i s t i n g of two words ( F i g u r e ^{I ) .} The l o c a t i o n of any f i e l d o r . g r o u p of b y t e s i s s p e c i f i e d by t h e a d d r e s s of i t s l e f t m o s t b y t e .

The programmer should b e aware of t h e s i z e of t h e NSSC-I1 being

A h a l f - A word i s a group of f o u r c o n s e c u t i v e b y t e s ; a double

The l e n g t h of f i e l d s i s e i t h e r implied by t h e o p e r a t i o n t o b e performed o r s t a t e d e x p l i c i t l y as p a r t of t h e i n s t r u c t i o n .

p l i e d , t h e i n f o r m a t i o n i s s a i d t o have a f i x e d l e n g t h , which can b e e i t h e r one, two, f o u r , o r e i g h t b y t e s .

When t h e l e n g t h i s i m -

When t h e l e n g t h of a f i e l d ^isn o t implied by t h e o p e r a t i o n code, b u t i s s t a t e d e x p l i c i t l y , t h e i n f o r m a t i o n i s s a i d t o have v a r i a b l e f i e l d l e n g t h . This l e n g t h can be v a r i e d i n one-byte increments.

Within any program format o r any f i x e d l e n g t h operand f o r n a t , t h e b i t s making up t h e format a r e c o n s e c u t i v e l y numbered from l e f t t o r i g h t s t a r t i n g w i t h t h e number 0.

Byte

[l 1 0 ;0 0 0 11

0 7

Hal fword

J K

1 1 01 0 0 0 1 1 101 0 0 1

0 7 E 15

Word

0 15 1b I 3 1 4 J1

\

Figure 1. Sample Information Formats

-3-

.

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2 . 2 ADDRESSING

, Byte l o c a t i o n s i n s t o r a g e a r e c o n s e c u t i v e l y numbered s L a r t i n g w i t h 0 ; each number is c o n s i d e r e d t h e a d d r e s s of t h e corresponding b y t e . group of b y t e s i n s t o r a g e i s addressed by t h e l e f t m o s t b y t e of t h e group.

d e f i n e d by t h e o p e r a t i o n . b i n a r y a d d r e s s .

l o c a t i o n s r e s e r v e d f o r s p e c i a l purposes.

A

3

14 The number of b y t e s i n t h e group i s e i t h e r implied o r e x p l i c i t l y The a d d r e s s i n g arrangement u s e s a 20 b i t

q

1

;i

d

T h i s set of main s t o r a g e addresses i n c l u d e s some

4

I

S t o r a g e a d d r e s s i n g wraps around from t h e maximum b y t e a d d r e s s t o a d d r e s s 0.

l a s t and p a r t i a l l y i n t h e f i r s t l o c a t i o n of s t o r a g e , and a r e processed w i t h o u t any s p e c i a l i n d i c a t i o n of c r o s s i n g t h e maximum a d d r e s s boundary, e x c e p t , p e r h a p s , s t o r a g e p r o t e c t i o n .

V a r i a b l e l e n g t h operands may be l o c a t e d p a r t i a l l y i n t h e

When only a p a r t of t h e maximum s t o r a g e c a p a c i t y i s a v a i l a b l e i n a given i n s t a l l a t i o n , t h e a v a i l a b l e s t o r a g e i s normally c o n t i g u o u s l y a d d r e s s - a b l e , s t a r t i n g a t a d d r e s s 0. An a d d r e s s i n g e x c e p t i o n i s recognized when any p a r t of a n operand i s l o c a t e d beyond t h e maximum a v a i l a b l e c a p a c i t y of an i n s t a l l a t i o n . Except f o r a few i n s t r u c t i o n s , t h e a d d r e s s i n g e x c e p t i o n i s recogn'ized only when t h e d a t a a r e a c t u a l l y used and n o t when t h e o p e r a t i o n is completed b e f o r e u s i n g t h e d a t a .

e x c e p t i o n causes a program i n t e r r u p t i o n .

The a d d r e s s i n g

2.3 INFORNATION PROCESSING ^!

Fixed l e n g t h f i e l d s , such as halfwords and double words, must be l o c a t e d i n main s t o r a g e on an i n t e g r a l boundary f o r t h a t u n i t of i n f o r m a t i o n . A boundary i s c a l l e d i n t e g r a l f o r a u n i t of i n f o r m a t i o n when i t s s t o r a g e a d d r e s s i s a m u l t i p l e of t h e l e n g t h of 'the u n i t i n b y t e s . example, words ( f o u r b y t e s ) must be l o c a t e d i n s t o r a g e s o t h a t t h e i r a d d r e s s is a m u l t i p l e of t h e number 4 . A halfword (two b y t e s ) m u s t have an address t h a t i s a m u l t i p l e of t h e number 2 , and double word

(eight bytes) m u s t have an a d d r e s s that i s a multiple of t h e number 8.

S t o r a g e a d d r e s s e s are expressed i n b i n a r y form. I n b i n a r y , i n t e g r a l boundaries f o r halfwords, words, and double words can b e s p e c i f i e d o n l y by t h e b i n a r y a d d r e s s e s i n which one, two, o r t h r e e of t h e low o r d e r b i t s , r e s p e c t i v e l y , a r e z e r o ( F i g u r e 2 ) . For example, t h e i n t e g r a l boundary f o r a word i s a b i n a r y a d d r e s s i n which t h e two low o r d e r p o s i t i o n s a r e z e r o .

For

-4-

, a

. .

1

^.

C

c:

... ._

.~ . . . - .

(15)

V a r i a b l e l e n g t h f i e l d r are n o t l i m i t e d t o i n t e g r a l b o u n d a r i w ,

and my

o t a r t on any b y t e l o c a t i o n .

.L W a d Word W a d

L I

D d l o W a d Daublo W a d

t

Figure 2. Integrr1,Boundrria for Halfwords, Words, and Dou blr Words

2.4 STORAGE PROTECTION

Memory i s p r o t e c t e d ( f o r s t o r i n g o n l y ) i n b l o c k s of 1 K = 1024 b y t e r . There is no f e t c h p r o t e c t i o n .

each b l o c k . CPU;

Memory Access (DMA).

be r e a d ( r r f e r t o paragraph

8.5.SD SSK,

and paragraph 3 . 7 . 3 , DMA).

An i n t e r r u p t w i l l set t h e s t o r a g e p r o t e c t key f o r t h e f i r e t b l o c k t o 01, This w i l l allow t h a CPU t o s t o r e in t h r f i r s t b l o c k and pre- vent DMA from s t o r i n g i n t h a f i r s t block.

All

o t h e r s t o r a g e p r o t e c t

kayo are

u n a l t e r e d

by

i n t e r r u p t s .

A

two b i t p r o t e c t key

is

a s s o c i a t e d w i t h

The f i r s t

b i t on p r o t e c t s t h e b l o c k a g a i n s t s t o r e s by t h e

The key i e s e t by t h e

SSK

i n s t r u c t i o n b u t cannot t h e eecond b i t on p r o t e c t s t h e b l o c k a g a i n s t e t o r e s by Direct

(16)

t

>

Storoge Address

SECTION I11 CPU

MAIN STORAGE

3.1 CENTRAL PROCESSING UNIT FUNCTIONS

A

The Central Processing Unit (CPU) (Figuie 3) contains the facilities for addressing main storage, for fetching or storing information, for arithmetic and logical processing of data, for sequencing instructions in the desired order, and for initiating the communication between

r - " - % Instrvctions

I v

I I

I Computer Voriable-

Ficld-Cength

I System I Fixed-Point

I Control 1 Operations Operotions

storage and external devices.

\ f

Flo,itiny Point Oper,ition

The system control section provides the normal CPU control that guides the CPU through the functims necessary to execute the instructions.

I

I I A

A

I I

L,--J

y 'I

1

!

Figure 3. Basic Concept of Central Processing Unit Functions

. . ..

(17)

'.

i ⁱ

4

S

t

Integer

-

ri- . f

'3

S .

3.2 REGISTERS

Integer

The CPU c a n a d d r e s s i n f o r m a t i o n i n 1 6 g e n e r a l r e g i s t e r s . The g e n e r a l r e g i s t e r s can b e used as i n d e x r e g i s t e r s , i n a d d r e s s a r i t h m e t i c and i n d e x i n g , and as accumulators i n f i x e d p o i n t a r i t h m e t i c and l o g i c a l o p e r a t i o n s . The r e g i s t e r s have a c a p a c i t y o f one word ( 3 2 b i t s ) . g e n e r a l r e g i s t e r s are i d e n t i f i e d by numbers 0-15 and a r e s p e c i f i e d by a f o u r b i t R f i e l d i n a n i n s t r u c t i o n .

a d d r e s s i n g m u l t i p l e g e n e r a l r e g i s t e r s by having s e v e r a l R f i e l d s . The Some i n s t r u c t i o n s p r o v i d e f o r For some o p e r a t i o n s , two a d j a c e n t g e n e r a l r e g i s t e r s a r e coupled t o -

g e t h e r , p r o v i d i n g a two word c a p a c i t y . I n t h e s e o p e r a t i o n s , t h e a d d r e s s e d r e g i s t e r c o n t a i n s t h e h i g h o r d e r operand b i t s and must have an even

a d d r e s s ; and t h e i m p l i e d r e g i s t e r , c o n t a i n i n g t h e low o r d e r operand b i t s , h a s t h e n e x t h i g h e r a d d r e s s .

The C P U can a d d r e s s i n f o r m a t i o n i n 4 f l o a t i n g p o i n t r e g i s t e r s . t e r s have a c a p a c i t y of o n e word ( 3 2 b i t s ) .

a r e i d e n t i f i e d b y the n u m b e r s 0-2-4-6 a n d a r e s p e c i f i e d b y t h e f o u r b i t K f i e l d i n an i n s t r u c t i o n .

i n d e x r e g i s t e r s

.

The r e g i s - The f l o a t i n g p o i n t r e g i s t e r s The f l o a t i n g p o i n t r e g i s t e r s cannot b e used a s 3 . 3 ARITHPfETIC AED LOGICAL U N I T

i

-7-

The a r i t h m e t i c and l o g i c a l u n i t can p r o c e s s b i n a r y i n t e g e r s of f i x e d l e n g t h and l o g i c a l i n f o r m a t i o n of e i t h e r f i x e d o r v a r i a b l e l e n g t h . 3.3.1 FIXED POINT ARITHMETIC

The b a s i c a r i t h m e t i c operand i s t h e 32 b i t f i x e d p o i n t b i n a r y word.

S i x t e e n b i t halfword operands may b e s p e c i f i e d i n ^most:o p e r a t i o n s f o r improved performance o r s t o r a g e u t i l i z a t i o n ( s e e F i g u r e 4 ) . To pre-.

serve p r e c i s i o n , some p r o d u c t s and a l l dividends a r e 6 4 b i t s l o n g .

Figure 4. Fixed-point Number Formats

Because t h e 32 b i t word s i z e r e a d i l y accomqodates a 1 6 - b i t a d d r e s s , f i x e d p o i n t a r i t h m e t i c can b e used b o t h f o r i n t e g e r operand a r i t h m e t i c and f o r a d d r e s s a r i t h m e t i c . This combined usage p r o v i d e s economy and per- mits t h e e n t i r e f i x e d p o i n t i n s t r u c t i o n set and s e v e r a l l o g i c a l opera-

tions t o b e used i n a d d r e s s computation.

and l o g i c a l m a n i p u l a t i o n of a d d r e s s components Thus, m u l t i p l i c a t i o n , s h i f t i n g , a r e p o s s i b l e . ^F.

c

.._... .. ..., . ^_.-^.-^{. . . .}..--...- . . ^,,,-7. ^I.--,-; 7 y * - c - c* -4-<*

... - ... . . . . . . .--- -.-- ... -.- . . . . .... . . . . .

(18)

I

MditiOnS, subtractions, multiplications, divisions, and comparisons are performed upon one operand in a register and another operand either

in a

register or from storage. Multiple precision operation

is

made convenient by the twos-complement notation and by recognition of the

carry

from

one

word to another. A word in one register or

a

double word

in

a pair of adjacent registers may be shifted left

or

right.

A pair of conversion instructions

-- CONVERT TO BINARY

and

CONVERT TO

DECIMAL

--

provides transition between decimal and binary radix (number base) without the use of tables. Multiple register loading and storing instructions facilitate subroutine switching.

3 . 4 DECIMAL

NUMBERS

Decimal numbers are represented by four bit binary coded decimal d i g i t s packed two to a byte (see Figure

5).

They appear in fields of variable 1ength.and are accompanied by a sign in the right-most four bits of the

low

order byte. Operand fields may be located

on

any byte boundary,

. .

Digit Code Sign Code 0

1 2 3 4 5 6 7 8 9

0000 + 1010

0001

-

¹⁰¹¹

0010

+

1100 0011

-

¹¹⁰¹

0100

+

¹¹¹⁰

0101

'+

1111 01 10

0111 1060 1001

Figure 5. Bit Codes for Digits and Signs

and may have a length up to

31

digits and sign.

in an operation may have different lengths.

a

byte (Figure

6)

and

of

variable length fields within storage results i n efficient use of storage, in increased arithmetic performance,

and

in

an

improved rate

of

data tranemission between storage and files.

Operands participating Packing of digit8 within

Highh-ordrr Byto Lw-ordsr Byto

. .

I

..-

Digit Digit Digit Diol? Sign

... .-.

Flgun 6. Packed DocimI Numkr Format

-8-

(19)

Docima1,numberr may a l r o appear i n a zoned format ar a rubrrrt of t h e e i g h t b i t alphanumeric character e e t (Figure 7 ) .

i r r e q u i r e d f o r character

ret

e e n s i t i v e 1/0 d e v i c e r .

' b a r carrier i t s s i g n

i n

t h e l e f t - m o r t f o u r b i t e of t h e

low

o r d e r b y t e ^* This r e p r e s e n t a t i o n

A

zoned format n u -

Figuro 7. Zoned D o c i d Number Format

I n r t r u c t i o n a are provided f o r packing and unpacking decimal numbers r o t h a t t h e y may b e changed from t h e zoned t o t h e packed format and vice versa.

3.5 LOGICAL OPERATIONS

L o g i c a l i n f o r m a t i o n

is

_handled ae f i x e d o r v a r i a b l e l e n g t h d a t a .

i r

o u b j e c t t o euch o p e r a t i o n s as comparison, t r a n s l a t i o n , b i t t e s t i n g , and b i t r e t t i n g .

It

When used as a f i x e d l e n g t h operand, l o g i c a l i n f o r m a t i o n can c o n e i e t of e i t h e r one, f o u r , o r e i g h t b y t e s and

I8

proceseed

in

t h e g e n e r a l r e g i s t e r s

(Figure

8).

A l a r g e p o r t i o n of l o g i c a l i n f o r m a t i o n c o n r i e t s of a l p h a b e t i c o r numeric c h a r a c t e r codes, c a l l e d alphameric d a t a , and ie used f o r communication w i t h c h a r a c t e r B e t s e n s i t i v e 1/0 d e v i c e s .

v a r i a b l e - f i e l d - l e n g t h format and can c o n s i e t of up t o 256 b y t e s ( F i g u r e 9 )

.

r i a h t b i t b y t e

a t

a

time.

This i n f o r m a t i o n h a s t h e It

ie

proceescd a t o r a g e t o r t o r a g e , l e f t t o r i g h t ,

an

Fisrd-Lrngth Logical Operand (Onr, Four, or Eight Bytra)

I

^Logier1^Data

I

Figure 8. f iwd-Length Logical Information

Varirblr-Length Logical Operand (Up

- -

to 266 Bytea)

- - - - --

Figure 8. Variablr-Length Logical Information

-9-

(20)

.

3.6 PROGRAM EXECUTION

The

CPU

program COnSi6tEJ of instructions, index words, and control words specifying the operations to be performed.

This

information residee

in

main storage and general registers, and may ba operated upon ar data.

3.6.1

INSTRUCTION

FORMAT

The length of an instruction format can be one, two, or three halfwords.

It

l e related to the

rider

of storage addresses necessary for the Operation.

reference to main storage.

storage address specification; a three halfword instruction provides two storage address rpecifications. All instructions must be located baric instruction formats.

An iasbruction consisting

of

only one halfword causes no

A

two halfword instruction provides one storage on integral boundaries for haY.fwords. .Figure

10

shows five The five basic Instruction formats are denoted by the format codes

RR, Bx, m, SI,

and

SS.

The format codes express, in general t e r m , the operation to be performed.

RR

denotes a register-to-register operation;

Rx, a

register-and-indexed storage operation;

RS ,

a register-and-rtorage 1 ( 1

operation;

SI,

a storage and ipmrediate-operand operation; and SS, a

storage-to-storage operation. An immediate operand

is

one contained ^I

wlthin the Instruction.

I

For purpores

of

describing the execution of instructions, operands are designated as first and second operands and, in the case of branch-on- Index instructions, third operands. These name8 refer to the manner

in

which the operands participate.

inrtruction format applies is generally denoted by the number following the code name of the field, for example, R1,

B1, L2, D2.

In each format, the firat inetructlon halfword c o n s i s t s of two parte.

The firrt byte containe the operation code (op code). The length and f o m t of

an

instruction are specified by the firet two bits of the operation code,

r

i

I

The operand to which a field in an

3.6.2

ADDRESS GENERATION

For addteesing purposes, operands can be grouped in three claeees:

explicitly addressed operands in main storage; immediate operands placed

u

part

of

the instruction e t r e a in w i n storage; and operands located i n the general regirters.

-10-

* .

(21)

Iw Fornot

RS

1 I

INSTRUCTION LENGTH RECORDING

INSTRUCTION INSTRUCTION FORMAT BIT POSITIONS

(0.1 1 LENGTH

00 01 10 11

One hrlfword Two halfword, Two halfword'

?reo halfword'

RR RX RS or SI

88

NOTE: NSSC-II instructions above the standard System/360 set may not adhere t o this instruction length format convention.

Flguro 10. Fivr Buic lnatrucdon Formats

-11-

(22)

To p e r m i t t h e r e a d y r e l o c a t i o n of 2rogram segments and t o p r o v i d e f o r t h e f l e x i b l e s p e c i f i c a t i o n s of i n p u t , o u t p u t , and working areas, a l l i n s t r u c t i o n s r e f e r r i n g t o main s t o r a g e have been g i v e n t h e c a p a c i t y of employing a f u l l a d d r e s s .

The a d d r e s s used t o r e f e r t o main s t o r a g e i s g e n e r a t e d from t h e f o l - lowing t h r e e b i n a r y numbers.

3.6.2.1 Base Address (B)

Base Address ^(B) ^{i s}^a2 0 - b i t number c o n t a i n e d i n a g e n e r a l r e g i s t e r s p e c i f i e d by t h e program i n t h e B f i e l d of t h e i n s t r u c t i o n .

f i e l d i s i n c l u d e d i n e v e r y a d d r e s s s p e c i f i c a t i o n .

b e used as a means of s t a t i c r e l o c a t i o n of programs and d a t a . t y p e c a l c u l a t i o n s , i t c a n s p e c i f y t h e l o c a t i o n of a n a r r a y and, i n r e c o r d - t y p e p r o c e s s i n g , i t can i d e n t i f y t h e r e c o r d .

p r o v i d e s f o r a d d r e s s i n g t h e e n t i r e main s t o r a g e . a l s o b e used for i n d e x i n g purposes.

The B The b a s e a d d r e s s can

I n a r r a y - The b a s e a d d r e s s The b a s e a d d r e s s may

3.6.2.2 Index (X)

Index (X) is a 20-bit number c o n t a i n e d i n a g e n e r a l r e g i s t e r s p e c i f i e d by t h e program i n t h e X f i e l d of t h e i n s t r u c t i o n . It is i n c l u d e d o n l y i n t h e a d d r e s s s p e c i f i e d by t h e RX i n s t r u c t i o n format. The RX format i n s t r u c t i o n s p e r m i t double indexing: i . e . , t h e i n d e x can b e . u s e d t o p r o v i d e t h e a d d r e s s of an element w i t h i n an a r r a y .

3.6.2.3 Displacement (D)

Displacerncnt (D) i s . a 1 2 - b i t number c o n t a i n e d and i s i n c l u d e d i n every a d d r e s s computation.

i n t h e i n s t r u c t i o n format The displacement p r o v i d e s f o r r e l a t i v e a d d r e s s i n g up t o 4095 b y t e s beyond t h e element o r b a s e a d d r e s s .

s p e c i f y one of many i t e n s a s s o c i a t e d w i t h a n element.

s i n g of r e c o r d s , t h e displacement can b e used t o i d e n t i f y items w i t h i n a r e c o r d .

I n a r r a y t y p e c a l c u l a t i o n s t h e displacement can be used t o I n t h e proces-

I n forming t h e a d d r e s s , t h e b a s e a d d r e s s and i n d e x a r e t r e a t e d as unsigned 20-bit p o s i t i v e b i n a r y i n t e g e r s . The d i S i J l acement i s s i m i l a r l y t r e a t e d a s a 1 2 - - b i t p o s i t i v e b i n a r y i n t e g e r . The Clirce arc' a d d e d a s 20 ^{b i t}b i n a r y numbers, i g n o r i n g overflow. Since every address i n c l u d e s a b a s e , he s u m i s a l w a y s 20 b i t s long. T h e a d d r e s s b i t s a r e numbered 12-31 corrc:sponding t o t h e numbering o f t h e base a d d r e s s and i n d e x b i t s i n t h e g e n e r a l r e g i s t e r ,

-12-

. .. .- _.

. . . - - . , . . . ..

(23)

’ . ’.

Y.

Add 7

, .!

9

Store ? 8 3 1 1 I2 10 I IS 16 14 1920 300 ₁₁

I

Execution of t h e s t o r e i n s t r u c t i o n s t o r e s t h e c o n t e n t s of g e n e r a l r e g i s t e r 3 a t a main s t o r a g e l o c a t i o n a d d r e s s e d by t h e sum of 300 and t h e low o r d e r 20 b i t s of g e n e r a l r e g i s t e r s 1 4 and 10.

3 . 6 . 3 SEQUENTIAL INSTRUCTION EXECUTION

Normally, t h e o p e r a t i o n of t h e CPU is c o n t r o l l e d by i n s t r u c t i o n s t a k e n i n sequence.

t h e i n s t r u c t i o n a d d r e s s i n t h e c u r r e n t PSW. The i n s t r u c t i o n a d d r e s s i s i n c r e a s e d by t h e number of b y t e s i n t h e i n s t r u c t i o n f e t c h e d t o a d d r e s s t h e n e x t i n s t r u c t i o n i n sequence. The i n s t r u c t i o n i s t h e n executed and t h e same s t e p s a r e r e p e a t e d u s i n g t h e new v a l u e of t h e i n s t r u c t i o n a d d r e s s .

An i n s t r u c t i o n i s f e t c h e d from a l o c a t i o n s p e c i f i e d by The program ^mayhave z e r o s i n t h e b a s e a d d r e s s , i n d e x , o r d i s p l a c e m e n t f i e l d s .

a d d r e s s component.

is t o b e used in forming t h e a d d r e s s , r e g a r d l e s s of t h e c o n t e n t s of g e n e r a l r e g i s t e r 0.

X n i t i a l i z a t i o n , m o d i f i c a t i o n , and t e s t i n g of b a s e a d d r e s s e s and i n d e x e s can b e c a r r i e d o u t by f i x e d p o i n t i n s t r u c t i o n s , . o r by BRANCH AND L I N K , BRANCH ON COUNT, o r BRANCH-ON-INDEX i n s t r u c t i o n s .

A s a n a i d i n d e s c r i b i n g t h e l o g i c of t h e i n s t r u c t i o n format, examples A z e r o i s used t o i n d i c a t e t h e absence of t h e c o r r e s p o n d i n g

A base o r i n d e x of z e r o i m p l i e s t h a t a z e r o q u a n t i t y A d i s p l a c e m e n t of z e r o h a s no s p e c i a l s i g n i f j - c a n c e .

of two i n s t r u c t i o n s and t h e i r r e l a t e d i n s t r u c t i o n f o r m a t s f o l l o w .

Execution of t h e ADD i n s t r u c t i o n adds t h e c o n t e n t s of g e n e r a l r e g i s t e r 9 t o t h e c o n t e n t s of g e n e r a l r e g i s t e r 7 and t h e sum of t h e a d d i t i o n i s p l a c e d i n g e n e r a l r e g h t e r 7.

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7.4.4

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2.4

3.5

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TABLE OF CONTENTS

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ARCHITECTURE

STRUCTURE

Ad

(B)

i 1

1

6

7 7 8

14

17

19

20

Iv

PrrasraDb 3.7.3

4.1

4 a 4

CONTENTS

Memory Accere

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Code

-

Number

Load

Add

20

28

36

40

46

48

0 TABLE OF

Ew!a?mh

DECIMAL

M o w

6.1

7

Mova

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61

62 64 65

75

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TABLE OF CONTENTS (CONTINUED) Paranra~b

7.4.4

7.4.6 7.4.6.1 8.1 8.1.1 8.1.2 8.2 8.2.1 8.2.2 8.4

8mSel 8.5.2

8.5.4 8.9.5 8.5.6 8.567 8.5.8 8.569 8.6 9.1 9.1.1 9.1.2

9.3 9.3.1 9.3.2 9.3.3 9.3A 9.3.5 ,9s3m6

9.3.') 9.3.8 9.3.9 9.3.10 9.3.11

Title

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Branch on Index

Branch on Index Low or Equal Execute

. ⁵ .

0 ^{TABLE OF}

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**9*5 Machine-Chack Interruption 10.1**

10 10.9 . ¹¹

13 10oSa14 **10*5.15 10.5**