Signal Description Direction
1GND 2GND AB## Address Bus MBIN Memory bank control in All signals are active-low!
3 +12V 4 +12V DB## Data Bus MBOT Memory bank control out
5 +12V 6 +12V EXEC Instruction is "Select" or "Select and Present" P --> I
7 -12V 8 -12V I/O Operation Signals IN Instruction is "Input" P --> I
9DPIN 10DPOT Utility Signals OUT Instruction is "Output" P --> I
11 12 Interrupt Signals PLSE Interface strobe P --> I
13 +5V 14 +5V DMA Signals RST Reset all interfaces P/C --> I
15MST 16 CLK 1Mhz timing reference P --> I
17MACK 18RD TYP1 Type-1 processor installed P --> I
19TYP1 20SLB SER Interface controller status P <-- I
21PFD 22MDIS IUR Interrupt request P <-- I
23AB08 24AB09 IOCL Synchronize IUR into the processor P --> I
25AB10 26AB11 PRIN Interrupt priority in I <-> I
27GND 28GND PROT Interrupt priority out I <-> I
29AB12 30AB13 IUA Interrupt acknowledge P --> I
31AB14 32AB15 IAR Interrupt address request P --> I
33 34 ECHO Transfer Complete P --> I
35STOP 36SACK IL1 Non-maskable interrupt (Vector 0002) P <-- I
37MBIN 38MBOT IL2 Non-maskable interrupt (Vector 0006) P <-- I
39DB00 40DB01 DPIN DMA priority in I <-> I
41DB02 42DB03 DPOT DMA priority out I <-> I
43 +5V 44 +5V STOP Stop processor P <-- I
45DB04 46DB05 SACK Stop acknowledge P --> I
47DB06 48DB07 PFD Power failure detected PSU --> System
49DB08 50DB09 SLB Select least-significant byte P/I --> I/M
51DB10 52DB11 MST Memory start P/I --> M
53DB12 54DB13 RD Read mode P/I --> M
55DB14 56DB15 MACK Memory acknowledge P/I <-- M
57EXEC 58IN
59GND 60GND
61IOCL 62OUT
63CLK 64SER
65IUR 66IL1
67IAR 68IL2
69RST 70IUA
71PLSE 72ECHO
73 +5V 74 +5V
75AB03 76AB04
77AB05 78AB06
79AB07 80AB00
81AB01 82AB02
83PRIN 84PROT
85GND 86GND
