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Testbeam Results for the Mu3e Scintillating Fibre Detector

6thBeam Telescopes and Test Beams Workshop 2018 Lukas Gerritzen

on behalf of the Mu3e Fibre Group:

A. Bravar, S. Corrodi,A. Damyanova, L. Gerritzen, C. Grab, D. Miranda, A. Papa

L. Gerritzen 2018-01-18 1

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The Mu3e Experiment at PSI

Search for the lepton-flavour violating decayµ+→e+ee+(in SM:BR<10−54)

• goal sensitivity<10−16 current: 10−12(SINDRUM)a

• muons decay at rest

aBRlimit at 90 % C.L.

• pe. m2µ ≈53 MeV

• e-tracks bent in 1 T

solenoid field L. Gerritzen 2018-01-18 2

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The Mu3e Detector

Target Inner pixel layers

Outer pixel layers Recurl pixel layers

Scintillator tiles μ Beam

Tracking: 4 Si Pixel Layers (HV-MAPS)

• high efficiency, spatial resolution

• thinned to 50 µm

→ ∼0.1 % X0per layer

See also talk by L. Huth

Timing: Scintillating Fibres and Tiles

• O(500 ps) (fibres);∼70 ps (tiles)

• background reduction and charge ID

• light detection with SiPMs

L. Gerritzen 2018-01-18 3

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The Mu3e Scintillating Fibre Detector

Setup

• 12 ribbons (1.6 cm×28–30 cm)

• 3 layers of 250 µm fibres

• right below second pixel double layer

• LHCb type: column array SiPMs

Requirements

• low material budget(<0.5 %X0,.1 mm)

• high efficiency

• timing<500 ps

• rates up to 250 kHz/fibre

L. Gerritzen 2018-01-18 4

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The Mu3e Scintillating Fibre Detector Up Close

electrical and thermal contact accommodates space for

pixel assembly

21

final: 128×0.25 mm = 32 mm

Hamamatsu S13552: column array SiPM: 128 cells, 250 µm×1.6 mm each

L. Gerritzen 2018-01-18 5

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SciFi Readout – custom ASIC: MuTRiG

mixed mode,≈50 ps t-stamps high impedance, opt. differential

Timing Threshold Energy Threshold

Timing Trigger Energy Trigger XOR Output

Time Energy

Coarse Counter 622 MHz

Fine Counter 32 x 50 ps Bins

0 16 31

TCC ECC

TFC

DiscriminatorOutputTDCAnalogueInput

1.6 ns Hysteresis

Tiles: both Thresholds Fibres: only Timing-Threshold

and Energy-Flag

“time mode”

STiC3.1 MuTRiG done outlook

number of channels 64 32

LVDS speed[Mbit/s] 160 1250

event size [bit] 48 47

time mode - 26

event rate / chip[MHz] ∼2.6 ∼20

time mode - ∼38

event rate / ch[kHz] ∼40 ∼650

time mode - ∼1200

power per channel[mW] 35 35

size[mm x mm] 5x5 5x5

L. Gerritzen 2018-01-18 6

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Fibres Under Study

Ribbons (30 cm×0.8 cm) with 2, 3 or 4 layers of 250 µm thick, round, double cladding fibres.

Kuraray

• SCSF 78 MJ with 20 % TiO2in glue

• SCSF 81 MJ with 20 % TiO2in glue

Nanostructured Organosilicon Luminophores

• NOL 11 clear and with TiO2 in glue

L. Gerritzen 2018-01-18 7

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Experimental Setup

• crossed fibres as 1 mm×1 mm trigger

• Hamamatsu S13552 (128 channels, trenches, column array SiPM)

• 32 channels readout per side with custom DRS4 board (Uni Geneva)

L. Gerritzen 2018-01-18 8

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Waveforms

L. Gerritzen 2018-01-18 9

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Light Yield

#photons per cluster, one side

clusters are defined as adjacent SiPM channels

L. Gerritzen 2018-01-18 10

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Spectra and Cuts

Determine amplitudes corresponding to number of photons using charge.

Charge is not used in the further analysis.

L. Gerritzen 2018-01-18 11

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Time Resolution

3 2 1tleft tright0  [ns] 1 2 3

counts

mean         441 ps core       338 ps base       626 ps Ncore/Nbase    2.00 fwhm/2.35 406ps

NOL 11, 3 layers, no TiO2

To study timing: look at difference between first photon left and right.

L. Gerritzen 2018-01-18 12

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Efficiencies (threshold 0.5 phe, N

Ch.

≥ 2 left and right)

[t±3σ]

NOL 11 are very efficient compared to SCSF

L. Gerritzen 2018-01-18 13

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Outlook – MuTRiG

BTTB5

• last generationSiPM column array

• last generationscifi ribbons

• STiCpredecessor of MuTRiG

BTTB6 and beyond

• final SiPM-like column array

• improved ribbon production + (NOL)

• MuTRiG

DRS4 wf (single fibre)

)/2 [ns]

- t2 (t1

10 5 0 5 10

events/98 ps

0 100 200 300 400 500 600 700 800

σ= (tl−tr) = 2.0 ns

STiC3.1: one side

hDeltaT36-48 p2 1405 p5 4326

deltaT [ps]

20000

150001000050000 5000100001500020000 200

400 600 800 1000 1200 1400

hDeltaT36-48 p2 1405 p5 4326 delta time ch 36 and 48

σ= (tl−tr) = 1.4 ns

DRS4 wf (clusters)

3 2 1tlefttright0 [ns]1 2 3

counts

mean         441 ps core       338 ps base       626 ps Ncore/Nbase    2.00 fwhm/2.35 406ps

σ= (tl−tr) = 0.4 ns

MuTRiG

X

σ = (tl−tr) = ?

L. Gerritzen 2018-01-18 14

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Summary

• NOL already very efficient and offer light yield comparable to SCSF-78MJ

• no significant difference between ribbons with and without TiO2(previous testbeams)

Fibre #Layers Eff. (±3σ) σfirstt1−t2[ps] #phe

78MJ, TiO2 4 0.96 702 24.6

81MJ, TiO2 4 0.93 617 13.2

NOL11, TiO2 2 0.89 511 11.9

NOL11, TiO2 3 0.93 427 18.2

NOL11, clear 3 0.96 408 16.9

NOL11, TiO2 4 - 426 23.1

NOL11, clear 4 0.97 432 22.4

L. Gerritzen 2018-01-18 15

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BACKUP SLIDES

L. Gerritzen 2018-01-18 15

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Data Rate and Clustering

event rate data rate

at 108stoppedµ/s [M/s] [Gbit/s]

SciFi detector 274

Scintilating Fibres (235k/s/fibre) 1083

SiPM columns signal (420 k/s/column) 1290 36.1 SiPM columns dark counts (∼300 k/s/column) 922 25.8

SiPM columns total 2211 61.9

clustering 20.0

clustering per side

t1t2t3t4

t'21t't'3

left side

right side

- on FPGA (FE)

match sides

t1t2t3t4

t'21t'3t'

left side

right side

track to cluster match

t1t2t3t4

t'1t'2t'3

left side

right side

- best timing: use

tracking L. Gerritzen 2018-01-18 15

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Efficiency for Different Thresholds

L. Gerritzen 2018-01-18 16

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Time Resolution: Different Fit Models

3 2 1

t

left

t

right0  [ns] 1 2 3

counts

mean         441 ps

core       338 ps

base       626 ps Ncore/Nbase    2.00

single         431 ps

exp gauss 2506 ps

exp gauss   319 ps fwhm/2.35 406ps

L. Gerritzen 2018-01-18 17

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MuTRiG

PLL_CLK: 640 MHz SER_CLK: 640 MHz SYS_CLK: 128 MHz SPI_CLK: 20 MHz Group

Arbiter L2 FIFO

Frame Gen.

8b/10b CRC PRBS

Serializer CLK Divider

SPI Control Reg.

Event Counter

Time Base Analog FE

TDC Event Gen. Channel

Arbiter L1 FIFO

x8 x8

x8 x8

Input

<0:7>

x8

Analog FE

TDC Event Gen. Channel

Arbiter L1 FIFO

x8 x8

x8 x8

Input

<24:31> x8

... ... ...

SER_DATA SER_CLK SDISDO SCLKCS Coarse

counterFine counter

PLL Ref. CLK Chip Configuration

x32 Ext. Trigger

Digital Logic Circuit

...

- UMC 180nm CMOS

- analog Front-End + TDC + digital part - fully differential analog front-end - high speed data link (1.28 Gbps) - external trigger

- event counter for each channel, separate data path

- configurable data structure

PRBS + 8b/10b at 1.28 GHz:

L. Gerritzen 2018-01-18 18

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