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(

western peripherals

TM

Division of

14321 New Myford Road • Tustin, California 92680 • (714) 730-6250 • TWX: 910 595-1775 • Cable: WESPER

(2)

0

MODEL TC-151 TAPE CONTROLLER LOGIC MANUAL

PUBLICATION NUMBER 91000505

REV A

western peripherals

14321 MYFORD ROAD TUSTINJ CALIFORNIA 92680

© 1981 by Western Peripherals, Inc.

All Rights Reserved

PRINTED IN U.S.A. AUGUST, 1981

(3)

TABLE OF CONTENTS

TITLE

Assembly Drawing, TC-151 Tape Controller Assembly Drawing, TC-151 PE Adapter

Assembly Drawing, TC-151 Tape Controller Assembly Drawing, TC-151 PE Adapter

Assembly, Cable, TC-151 PE BD Inter Schematic, TC-151 Tape Controller Schematic, TC-151 PE Adapter

Schematic, TC-151 Tape Controller Schematic, TC-151 PE Adapter

LSI-11 Priority Jumper PROM Set, TC-151, NRZ

PROM Set, TC-131/TC-151, PE

Modification Drawing, TC-151 Configuration "A"

Modification Drawing, TC-151N Configuration "A"

Modification Drawing, TC-151 Configuration "C"

Modification Drawing, TC-151N Configuration "D"

Notes

Appendix A - Std Tape

60000619

60000627

60000866

60000874

62000419

75000547

75000554

75000778

75000786

76000223

18001511

18001321

79000691

79000717

79000931

79001194

(4)

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REVISIONS

I

LTR

I

DESCRIPTION

I

DATE --t 0 , ~ - -~, n I I

A PRODlJC.TIOl-l RELeA'5E 1,

/:.iJ(:;_

CABLEDA~\.l NO./LENC:.T\-1 TABULATION --- ---·---~~---,---- DA 5H DIM.A (IN lt-.ICHE'5) R.EIV\ARKo

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(2)

MARK. Pl\"k I NUrvl6f:\:>., DA ~H NUMBER. ANO L.A TE 5T REV --- LTR \/Vl-H:RE: ul\OWN U';:,\l'-lt:; C.ONTR.A'<:>T\N(,. IMK

Tl-\\ S \ S A TABULA T f:'. D DRAV'J H'1 G SEE Tl\B. A\:iOVE

IA\ llSHOP GRAPHICS/ACCUPAlSS

"W flEOROER NO. A 8454

TOLERANCES lJNl£SS OTHERWISE SP£Clfl(O FRACTIONS DEC ANGLES

..£:::&._western peripherals

~ TUSTIN, CALIFORNIA

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151

t-'. r:.

APPROVALS DAT.:.

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(13)

CPU BUS

CPU Bus Transceivers TM-11 Address Detector Data Latch

TABLE OF CONTENTS TC-151 SCHEMATIC

CPU Vector Jumpers and Gate Bus Signal Receiver

Reset Logic

PIO Address Latch

PLA Bus Sequencer NXM Timer/Latch

Control Line Drivers

Bus-Master Control Bus Priority Logic

DATA PROCESSOR

2901 Data Processor Write Byte Control

Literal Gate

Control Pulse Decoder Destination Decoder Source Decoder

Indicator LED's

"A" Latch

"B" Latch

ADDRESS PROCESSOR

Condition Test Registers Condition Test Select D-Bus Test Select

Micro-Interrupt Vector RAM's

PAGE 1

2

3

4

5

6

7

(14)

TABLE OF CONTENTS (CONTINUED)

TITLE

Micro-Interrupt Control

2910 Instruction Multiplexer 2910 Program Address Processor PIO Vector Gate

Timer Bit Generator

Controller Clock Generator

Data Buffer FIFO (P/O Data Processor)

Control Store ROM's (0-511)

Control Store ROM's (512-1023)

TAPE INTERFACE

Tape Write Clock Generator

Tape Unit Cormnand Register & Driver Unit Select Decoder & Driver

Write Data Register & Driver

Tape Status Terminator & Gate Tape Unit Select Register Parity Generator & Control PE Parity Gate

NRZI Read Register Tape Control & Status Re.ad Line Terminators Read Strobe Interrupt

PAGE 8

9

10

11

12

13

14

15

16

(15)

TABLE OF CONTENTS (CONTINUED)

PE READ BOARD PE Data Gate PE Drop-Out Gate PE Parity Control PE Status RDM PE Status Latch

PE Reference Divider PE Phase Comparator

PE Read Activity Detector and Control

PE Voltage Controlled Oscillators PE Clock Selector

PE Read Register PE Window Counter PE Deskew Register

PE Sequencer ROM's

PE Deskew Buff er Timer

PAGE 1

2

3

4-6

7-9

7

(16)

COt.JTHOL A r · - - - .

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(17)

REVISIONS

LTR DESCRIPTION DATE APPROV£0

106

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