Chapter 7 Conclusions
I prithee,
Remember I have done thee worthy service, Told thee no lies, made thee no mistakings, serv’d Without grudge or grumblings.
William Shakespeare The Tempest
An integrated circuit whose design is correct logically still may not function as in-tended if the system violates some of the underlying electrical constraints. Analyzing an entire chip can be difficult, however, due to its size. Design of a CAD tool to automate power and ground checks requires careful attention to the tradeoffs between speed and accuracy for each component.
For resistance extraction, a simple extractor that uses the standard square-counting approximation is best suited for power supply analysis. This method is surprisingly accurate, giving nearly the same results as finite element analysis in a fraction of the time. Even when compared to a fairly elaborate finite element extractor that used a library of previous solutions, the simple method is still two orders of magnitude faster.
In CMOS current estimation, the speed-accuracy tradeoffs surround time and pattern dependence. The design’s maximum current consumption cannot be calculated without trying most or all of the input patterns; such current estimation is much too expensive to perform on large circuits. Instead, my estimator is based on the switch level simulator
Rsim. Estimating currents with Rsim allows the designer to see how her circuit performs under real operating conditions and to test particular patterns that seem to be causing problems. Each event inside Rsim produces a triangular current pulse whose rising and falling edges depend on the slope of the gate’s inputs and the intrinsic delay of the gate’s output. These triangular pulses provide a reasonable approximation to the actual current waveform and can be produced and manipulated quickly. Pulses are also produced for the image currents that flow into the substrate. Experiments indicated that ignoring these image currents entirely led to an unacceptably inaccurate current distribution, but that they could be estimated fairly easily using a simple algorithm based on each node’s bounding box.
For ECL, there is also potentially a tradeoff to be made in selecting a current pattern or patterns; although the current magnitude is fairly constant, its distribution across the design varies with the input state. After describing a static estimator that finds and traces currents through the system, I showed that the current pattern is relatively insensitive to the circuit state; perturbations in the voltage and current distributions are minor, localized effects. A single current pattern is sufficient for ECL designs, making the resistance-current network fast to solve.
Given a tractable resistance network and current pattern, the linear solver must effi-ciently solve the system. I investigated three techniques for partitioning the network into smaller, more easily solved sections. First, subnetworks that form trees can be pruned from the graph and replaced by current sources with values equal to all the current in-jected in the tree. Second, simple configurations of loops can be solved using Kirchoff’s Voltage Law. Finally, sections of the network that form long series chains can be replaced by a single resistor with current sources at either end. Once all these simple subnetworks have been removed, the remaining core system can be solved using standard sparse matrix techniques, and the subnetwork voltages can then be back-annotated.
The key to this system is making the individual components operate correctly in tan-dem. The resistance extractor had to produce a network that contained the essence of the power distribution system, yet was still amenable to solution. The two current estimators needed to produce current profiles that accurately modelled the system’s activity, but were not too complicated to produce or to use. The linear solver had to be tailored to
capitalize on the special topologies of power networks and efficiently handle the most common configurations. With each part tailored to mesh with the others, Ariel provides insight for entire designs efficiently and accurately.
Although Ariel is a usable system now, there are both changes and extensions to the existing system that would enhance its utility. The biggest obstacle to analyzing chips of arbitrary size is the memory usage of the resistance extractor; because it flattens the power bus before extracting it, it is quite profligate in memory use. Extraction without flattening is not an easy problem, however. Hierarchical extraction is quite difficult unless cell overlap is extremely restricted; such restrictions are a nuisance to designers and inconsistent with Magic’s philosophy. Incrementally flattening a section, then extracting it is also not trivial; the extractor must determine which rectangles in a region correspond to the power bus (or else extract everything), it must produce the correct resistance even for rectangles that are intersected by the region boundary, and it must correctly assemble the parts.
There are several areas in current estimation that deserve additional attention. To date, no entirely satisfactory method of estimating currents for CMOS circuits has been found. The probabilistic methods of Burch produce expected instead of peak voltages and currents for the system, while my simulation based approach is pattern dependent. A ideal approach would produce currents that near worst case and avoid gross overestimation for circuits with limited activity.
The next major extension will be providing current estimation for BiCMOS. The fastest BiCMOS circuits may use ECL configurations for critical paths and MOS circuits for less critical ones in order to save power. Operating ECL circuits in a noisy MOS environment will accentuate the need for power supply noise analysis. The biggest challenge in current estimation for these designs is correct analysis of hybrid circuits, where neither a distributed RC tree model nor a current steering model is entirely accurate.
Finally, I would like to develop a useful set of postprocessing tools. The voltage and current profiles that Ariel produces are basically raw data; what the designer would really like to know is how the system’s power noise is going to affect his particular design. Does a given circuit have sufficient noise margin to tolerate the supply noise? How can the placement of cells be modified to equalize the current patterns? Can the circuit timing be
modified to redistribute power consumption more evenly across the clock cycle? These types of questions combine the raw data calculated by Ariel with additional concerns about the circuit, about the layout, and even about the underlying logic. This analysis is critical for fullest utilization of power supply analysis.