The decisions concerning the stores for MU5 were taken in 1968. This was before large capacity high speed semiconductor stores had become feasible, and the most promising development among the analogue store technologies was plated-wire. Plessey had a plated-wire store under development with an expected cycle time of 250 ns. Unfortunately the price of £16 750 per 2K stack of 128-bit words was restrictive.
MU5 was being designed as a machine to run very large programs, and support the order of hundreds of interactive terminals. Although the terminal activities would be very variable, their store requirements were not be expected to be less than thousands of words. Thus a total store requirement of several million words was anticipated. Clearly it could not be by plated-wire store only. In fact, for this size of store, even medium speed (2.5 J.ls) core store available from Philips at £41 500 per 128K stack of 32-bit words was too expensive. A store hierarchy with some plated-wire store to obtain performance, and drum or fixed-head disc to obtain capacity was the only solution.
Ideally the store at the fast end of the hierarchy should be large enough to accommodate the active parts of several interacti ve jobs, and a background job. If an Atlas type of 'one-level' store with demand paging is to be used, the transfer time for pages must be matched to the machine speed.
Consider an MU5 with a 10 MIPS instruction rate and a modest sized main store backed up by a drum with a 20 ms revolution time. Even with very high packing density on the drum, page transfers would cost on average 10 ms. This time would be equivalent to 100 000 instruction times. If a page size of 1K bytes was used, then for 75% CPU utilisation to be achieved, a program must obey 300 instructions for every byte of each new page brought in to store before requiring further new pages.
Clearly, this intensity of CPU usage would not apply to the pages that might be considered to be the active part of a program such as those containing
(1) the frequently used facilities and working space of a compiler
(2) an array to which a simple cyclic algorithm applies unless, of course, they could simul taneously fit into store.
Therefore, the conclusion was that if the plated-wire store is not big enough to accommodate the active parts of several jobs, an intermediate store, very much faster than the drum (for demand paging) , is needed between the two.
This line of thought has resulted in MU5 having a 'one-level' store which maps on to a hierarchy of three levels as shown in figure 2.2. The CPU operates on the Local Store and pages are brought on demand from either Drum or Mass Stores. They are rejected first to Mass and later to Drum. In practice this means that bulk of the paging traffic is between Mass and Local and residual traffic to Drum is at a bearable level. The actual !mplementation uses fixed-head disc but it is convenient to refer to it as a Drum to avoid confusion with the other discs in the system which are used for file storage.
The 'one-level' store of MU5 contains all the working space and files needed by the current terminal users and the active background jobs. Most of the files are stored on further large capacity discs, or archive discs or tapes. Thus the full storage hierarchy has at least two more levels than are shown in figure 2.2.
Drum (10 Mbytes)
Mass (1 Mbyte)
Local
- - - -... ---~ (128 Kbytes) ~---""---'
Figure 2.2 The Store Hierarchy 2.5 THE EXCHANGE
The data routes needed to implement the store hierarchy and the mUlti-computer connections are extensive. To increase the flexibility and allow scope for future development it was decided to generalise these connections into a highway system known as the 'Exchange' into which all the storage devices and computers of the MU5 complex are connected. This Exchange has been buil t as an integral part of the MU5 Project using basically the same technology as that used for the MU5 Processor. Logically it is a multiple-width OR gate operated as a packet switching system at the star point of the interconnections. This configuration involves only a very short common path for transfers between the various units and was chosen in preference to a distributed highway or 'bus' system in order to accommodate the high data rate associated with paging transfers. Thus transfers can occur at a rate of one every 100 ns, and each can involve a 64-bit data word together with address and control bits.
As an example of the use of the exchange consider the paging transfers between the Mass and Local stores which are organised by a Block Transfer Unit (BTU) attached to the Exchange. When MU5 requires a block of data to be transferred from the Mass Store to the Local Store, it writes into the BTU, via the exchange, the starting addresses for the transfer in each store, together with the block size and start command.
The Processor is then free to continue computation, while the
BTU generates the necessary requests, via the Exchange, to the Mass and Local Stores to carry out the transfers. Reading from a store involves two Exchange transfers, one in which the address is sent to the store, and one in which data is returned. In between these two transfers, however, the Exchange is free to carry out transfers between other units in the system.
The addressing sch.eme used for the Exchange allows up to 16 units to be accommodated, although technological considerations have limited the actual number of units to a maximum of 12. The units actually connected are shown in figure 2.3 The mu5 machine has not been previously mentioned.
It is a machine designed as the bottom end of the range. In the MU5 complex its role is to provide a graphics work station.
The overall system organisation shown below is discussed again in Chapter 9. First the technology used and the detail design of the MU5 processor are described.
w t9 Z «
::c u X w
Mass Store
Disc Control Unit
Block Transfer Unit
Performance Monitor
Engineers' Console
ICL 1905E
mu5
PDP-11/10
... ---Fixed-head Disc
I---VDU
Printers ... --Readers
Exchangeable Discs
On-line Consoles ... ~-Large Disc
Other Computers
Figure 2.3 The MU5 Multi-computer System