STORAGE TECHNOLOGY

As in any large computer system, a number of different storage technologies are used in MU5 in order to provide an economic balance between speed and capacity. Thus at the fastest level in the hierarchy ( figure 3. 14) associa ti vely addressed integrated circuit stores are used, while the main storage unit associated with the MU5 Processor, the Local Store, uses plated-wire technology. At the next level in the hierachy is the Mass Store, a 2.5 l.lS cycle-time core store, and beyond that is the Fixed-head Disc Store, which incorporates a Disc Transfer System capable of organising data transfers through the Exchange between anyone of up to four discs and the Mass or Local Stores. These are high-speed discs offering a limited capacity of about 10 Mbytes. Bulk file storage is therefore provided on other computers in the complex.

Transfers of information between the integrated circuit stores and the Local Store are controlled entirely by hardware under normal running conditions, while transfers between the Local Store and the rest of the hierachy are controlled by software (section 9.3).

3.2.1 The Local Store

The MU5 Local Store consists of four plated-wire memory stacks each containing 4096 12-bit words (64 data bits + 8 parity bits), and having a 260 ns cycle time. Plated-wire stores are essentially 2-D systems and each of the stacks of the MU5 Local Store is internally organised on a 2048 144-bi t word basis as shown in figure 3.15. No parity checking is performed within the store and so no distinction is made between data and parity bits. The stacks are individually controlled by timing circuitry in the Local Store Interface logic (section 6.3) which connects the stacks with SAC and the Exchange, so that under normal running conditions the stacks are interleaved and successive accesses to separate stacks may be overlapped to give a higher overall access rate. In the event

of a hardware failure in one or more stacks, a Fail-soft

I L ___________________________ Processor J

Figure 3.14 Storage Technologies in the MU5 Sysytem The store is constructed in a 144-bit wide arrangement mainly in order to reduce the number of word drivers required

for a given amount of storage (these circuits drive very much more current than the digit drivers, and are therefore much more expensive), but advantage can be taken of this fact when

serv~c~ng 128-bit word requests from units within the Processor. By setting the appropriate control digit when a request for an even-addressed 64-bit word is made, the corresponding odd-addressed 64-bit word (which is of necessity available in the Data Buffer) is automatically copied into the Output Buffer 50 ns after the even-addressed 64-bit word, and the two halves of the 128-bit word can be returned to the requesting unit in rapid succession.

Digit Drivers

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Figure 3.15 Internal Organisation of a Local Store Stack A write request begins with a normal read phase, but before the contents of the data buffer are written back into store, the appropriate half is overwritten with new information.

Although there is no reason in principle why 128-bit word wri te requests should not be organised on a similar basis, there seemed no justification for incorporating such a facility at the time when the specification of the stores was

agreed with the manufacturer. In the light of experience gained during the subsequent design of the Processor, particularly with regard to the implementation of the store-to-store orders (section 7.4), there might have been some justification for its inclusion.

3.2.2 The Mass Store

The Mass Store interface logic allows up to four individual stores to be connected, but as a result of cost considerations, only two are connected. These stores are fairly straightforward 2.5-D core stores, each containing 128K words of 36 bits (32 data bits + 4 parity bits). The interface logic interleaves addresses to allow access to 64 data bits in one cycle, and also contains fail-soft logic which re-orders the addresses and allows the system to operate at reduced efficiency in the event of a hardware malfunction in one of the stores.

3.2.3 The Fixed-head Disc Store

The Fixed-head Disc Store developed for use as part of the MU5 complex is designed to accommodate four 'head per track' disc units linked to the Exchange via a Disc Transfer System. The first two disc units each contain eight 12 in. diameter rec'ording surfaces with 64 t.racks per surface. Data bytes are recorded in parallel on eight tr~cks in blocks of 1024, and each 20.5 ms revolution gives access to 37 blocks. The total capaci ty is thus 2.4 Mbytes per unit. The recording code is Modified Non-Return to Zero (NRZI) recorded at a constant bit frequency of 2.2 MHz. The maximum packing density is 1520 bits per inch ~n the inner track and the data rate is 1 byte every 450 ns [11]. The 'programmers' would have been happy to accept a system engineered to a less exacting standard, and to sacrifice some capacity for the convenience of having 32 blocks per revolution. The task of computing addresses of empty blocks, for example, is greatly simplified if the total number of blocks is a power of 2. (The positions of empty blocks are recorded in a bit list and the positions of bits in this list are used in the computation.) The 'engineers' were concerned to push the limits of performance, however, and to maximise the storage capacity.

The limit on information packing density in any hig~­

performance recording system is usually imposed by the timing variations which occur between writing and read-back, and these are of two distinct types, 'skew' and 'peak shift'. Skew is a long term phase variation on read-back between parallel tracks which were initially recorded using the timing from a common 'write clock'. The major contributions to skew in a

flying head system are the positioning accuracy of the retractable heads, variations in head inductance, differing cable lengths associated with individual heads, delays in the selection and read-back circuits, and gyro-precession of the rotating surface. On the disc used in the MU5 system, a figure of 250 ns was specified by the manufa9turer for the maximum skew between heads using a common write and read amplifier.

Peak shift arises from the super-position of read-back pulses at high packing densi ties and the amount of shift is dependent upon the pattern. Thus, unless adaptive writing techniques are used, this shift must be considered as purely random. On the MU5 discs, the worst-case peak shift is 3% of one bit period (equivalent to approximately 14 ns) at 1500 flux reversals per inch, rising to 25% at 3000 flux reversals per inch. Further random timing variations occur due to noise in the read-back channel. These are usually circuit dependent and are of the order of 20 ns in the MU5 system.

Thus skew is the dominant effect and in most. systems leads to the adoption of self-clocking codes such as Phase Modulation, Frequency Modulation and Delay Modulation. The conventional NRZI detection system cannot deal with skew of this magnitude, but, by use of a 'Self-Phasing' technique, the effect of skew can be reduced to acceptable levels. In this situation the NRZI recording code yields a higher bit-packing density than any of the three self-clocking codes and was therefore adopted for use in the MU5 system. (More recent commercial disc systems employ different techniques, using block codes, which allow even higher densities to be achieved. )

The Self-Phasing system operates by measuring the skew on each data track at the start of every data block and holding its value constant throughout the reading of the block. Since the block is only a small proportion of a revolution, the gyro-precession effects can be neglected. The measurement is per formed on a preamble pattern of 5 successi ve bits (00100) recorded in NRZI format on each track immediately prior to the normal data. This isolated 1 does not undergo any peak shift and can therefore be used for accurate skew measurement.

The measurement is carried out by digital techniques and permits a total skew of two bit periods, equivalent to gOO ns at 1500 bits per inch. The value of skew is held as a 3-bit binary number, thus dividing the two-bit period into eight separate skew values and allowing the skew to be measured to within 112 ns. When this is used to re-align the parallel data streams, a margin of 337.5 ns remains to accommodate peak shift and other dynamic timing variations.