A Structure That Can Incorporate New VLSI Quickly Advances in VLSI technology have resulted in performance and complexity

doubling every 2 to 3 years (Fig. 1-13). As an example, Intel Corporation's 8008 microprocessor, introduced in 1972, had a 30-lts average instruction execution time and was able to address a maximum of 16K bytes of memory. In 1982, Intel introduced the iAPX 80286 microprocessor, which has an average instruc-tion time of less than 1 itS and is capable of addressing a maximum of 16M bytes of memory. This technology explosion presents the system designer with the opportunity to design systems that have lower cost, higher performance, increased density, and greater reliability. But it also means quick obsolescence for systems that are not designed to permit the incorporation of future gener-ations of VLSI components. The system designer has the challenge of creating competitive systems that can easily assimilate successive generations of VLSI technology.

Historically, new VLSI components required new system designs, especially for new microprocessors. Designers would implement new system boxes each time a new microprocessor was introduced, which meant completely new mem-ory, I/O, and microprocessor board designs. The new designs were dedicated to supporting only a few functions with very basic and limited I/O. There was very little flexibility in the design to handle future VLSI technology or new peripherals without a major redesign. It became clear that a universal system box was needed; it would permit the use of previously designed memory and peripheral modules. From this exercise came the Multibus system bus, the first

standard microprocessor system bus, and its family members: the iSBX bus, the Multichannel bus, and the iLBX bus.

In this age of rapid technological change, the use of standard system struc-tures helps designers to quickly incorporate new VLSI technology into both new and old designs. They do so by tying the new VLSI devices to solid universal interfaces which are the gateway to all system resources such as memory and peripherals. The system must be developed in a functionally partitioned man-ner. Each of the functional units may be designed with the best technology available for that particular task and to interface to the system bus standard.

When future generations of VLSI devices permit it, a superior replacement functional unit can be designed provided it meets the interface standard. Since the interface remains unchanged, the new unit can replace the old one and minimize the impact it has on the other functional units in the system.

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FIGURE 1·13 Chart of VLSI density versus time.

20 THE MUL TIBUS FAMILY OF BUS STRUCTURES

Success in adapting future VLSI devices to microprocessor-based systems is measured by the effectiveness of the system's organization in alleviating the highly irregular structures of past and present microprocessors. The key lies in so defining the system bus structure that it is decoupled from any particular VLSI device. It must be architecture-independent; that is, it must be flexible enough to support many different families of VLSI devices. It should not have special signals that only one device supports. However, the interface must be similar to typical VLSI component interfaces to minimize the extra transistor-transistor logic (TTL) required to convert the component interface to the uni-versal interface. The board designer can design the VLSI device to the uniuni-versal bus interface provided the new device has the ability to communicate quickly and easily with the rest of the system.

As an example, let us examine a three-board system: a CPU board based on a 5-MHz Z80,⁵ a memory board, and a disk controller board. Assume that in the next design, a new CPU board is needed to get higher performance. The system designer needs to have the freedom to build an 8-MHz 80286-based CPU board. A properly defined bus structure would permit this new micropro-cessor board, which operates 10 times faster, to replace the old micropromicropro-cessor board without affecting the rest of the system. The memory and disk controller boards would not have to be modified or replaced.

Another goal of a bus structure must be longevity. One way to achieve lon-gevity is to support many different types of microprocessors and other VLSI devices over a 10- to 15-year lifespan. This requires that the bus structure sup-port generic microprocessor attributes such as memory address space, I/O address space, some form of mutual exclusion, interrupts, different widths of address and data lines, and multiple-bus master-control capability. The bus must also be independent of microprocessor, memory, and I/O device speed.

The Multibus system bus provides a very basic set of generic functions which support a wide range of microprocessor families. Two data path widths permit the use of both 8- and 16-bit microprocessors. That includes a very wide range of 8-bit microprocessors such as 8080, Z80, 6800, and 8088. In the 16-bit world, there are Multibus-based SBCs with 8-MHz 80286s, 8-MHz 68000s, and 8-MHz Z8000s. Addressing is flexible; it permits the choice of 64K bytes, 1M byte, or 16M bytes of memory address space. Separate I/O address space, which can be either a 256K- or a 65K-byte location, is also supported.

In applications in which the microprocessor requires more bandwidth from the system bus than it can deliver, the iLBX bus provides an alternative. Micro-processor memory bandwidth needs have increased at a greater rate than mem-ory subsystems have. The system bus which connects the two modules together can easily become the bottleneck. One solution is to use two buses in the system:

SZ80 is a trademark of Zilog Corporation, Cupertino, California.

one bus for execution (which must be very tightly coupled to the microproces-sor-memory subsystem pair) and a second bus for system communication and data movement. The iLBX bus provides this tightly coupled connection. The iLBX bus expands the local memory of the SBC, saving system bus bandwidth and supporting multicomputing architectures that require multiple SBCs with more memory than can fit on a single board.