iSBX I/O Bus
4.4 BUS OPERATION OVERVIEW
4.5.2 Signal Line Characteristics
The rise and fall times of all signals on the bus must not exceed the following limits. (This is not part of the specification but is a good practice to follow.)
Rise time, ns Fall time, ns
Totem pole Three-state 10
10
10 10
The settling time for all commands, Multimodule clock and interrupt request lines after a transition, is zero. The ringing on these lines cannot go beyond the noise immunity levels. These control signals are used to determine the state of the bus, and ringing beyond the noise immunity levels could cause system fail-ures. Address, chip select, MWAIT*, and data lines can ring beyond the noise immunity levels; the only requirement is that they be stable for their setup times. The setup, hold, and signal ringing are summarized in Fig. 4-17.
4.5.3 Bus Power Specification
All power supply voltages are
±
5 percent at the iSBX bus interface.148 THE MUL TIBUS FAMILY OF BUS STRUCTURES
Maximum
Minimum Nominal Maximum current,
voltage, V voltage, V voltage, V A
+4.75 +5.0 +5.25 3.0
+11.4 +12.0 +12.6 1.0
-12.6 -12.0 -11.4 1.0
GND 6.0
Note: Per iSBX bus interface on the baseboard.
4.5.4 Temperature and Humidity Limits
All bus parameters and specifications must be met within the following tem-perature and humidity limits:
Temperature 0 to 55°C (32 to 131°F); free moving air across iSBX Multi-modules and baseboard (200 LFM recommended)
Humidity 0 to 90% maximum relative (no condensation); 25 to 40°C (77 to 104°F)
COMMAND* HIGHMIN
GND RINGING
MAXIMUM 1 HIGH
GND ADDRESS
DATA 50 ns MINIMUM
30 ns MINIMUM LOW
GND
MWAIT*
---4~~~~====~~----~~---GND
o ns MINIMUM
READ[_HI_G~H==========~~----~~---+~~~==~---_GND
DATA
---..
~L\O~W~
________~~~~======~--- GND
FIGURE 4-17 Setup, hold, and ringing summary.
30g of force 11 ms in duration three times in three different planes (recommendation only)
Vibration3
4.5.5 storage
Sweeping from 10 to 50 Hz and back to 10 Hz at a distance of 0.010 in (0.025 mm) peak-to-peak lasting 15 min in each plane.
Temperature -40 to 70°C (-48 to 158°F)
Humidity 5 to 95% maximum relative (no condensation) Shock3 30g (recommendation only)
Vibration3 l.Og
4.5.6 Bus Timing
In this section all the detailed timing specifications on the iSBX bus are described; they are summarized in Table 4-2. For clarity, the timing diagrams in this section show only minimum or maximum values required for each parameter. The bus timing specification summary table should be referred to for complete minimum and maximum information. The timing diagrams show how all of the parameters are defined in relation to the signals involved. All timing is measured at 0.8 V for a low and 2.0 V for a high with full loading capacitance CL .
READ OPERATION
A read operation transfers data from the iSBX Multimodule port to the micro-processor on the baseboard. The lines involved and the timing specifications are shown in Fig. 4-18. The baseboard must first drive the address lines, MA2 to MAO, with a valid address in a minimum of 50 ns (tI ) and a valid chip select, MCSl* or MCSO*, in a minimum of 25 ns (t7) before the IORD* signal goes active.
If the read cycle is a full-speed (noninterlocked) type of data transfer, the iSBX Multimodule board must access the addressed port data and drive the data lines with valid data in less than 250 ns (t4). The I/O read command must be active in a minimum of 300 ns (t3)'
If the read cycle is an interlocked type of data transfer, the iSBX Multimode has a maximum of 75 ns (tI9 ) to drive MW AIT* low. The iSBX Multimodule board must complete the operation by driving the data lines with the accessed port data in a maximum of 4 ms (tl7)' There must be a setup time of at least 0 ns (t24 ) of valid data before MWAIT* can be driven high.
3Intel iSBX specification only
150 THE MUL TIBUS FAMILY OF BUS STRUCTURES
TABLE 4·2 ISBX Bus Timing Specification Summary
Symbol Parameter Minimum
t6 Time between read and/or write
t7 CS stable before CMD 25 os
ts CS stable after CMD 30 ns
t9 Power-up reset pulse width 50 ms tlO Address stable before write 50 ns tll Address stable after write 30 ns
tl2 Write pulse width 300 ns
aRequired only if WAIT. is activated.
"If MWAIT. is not activated.
ero
be specified by each iSBX Multimodule board.dRequired in cycle-steal mode and for last operation in burst mode.
Maximum
In both read operations, the data is strobed in by the baseboard and the com-mand is driven high. The iSBX Multimodule board must put the data lines in a three-state condition (the lines are floating with no devices driving them) in less than 150 ns (ts). The baseboard must hold the chip select line active for a minimum of 25 ns (ts) and the address line a minimum of 30 ns (t2).
WRITE OPERATION
A write operation transfers data from the baseboard to the iSBX Multimodule port. Timing for a write operation is shown in Fig. 4-19. The baseboard initiates the write operation by driving the address lines with a valid address in a
min-~ K
~t2-MCS(N)*
~ I
It8
-. t 19 t 1 7
-
---MWAIT*
-
I t24 14-t3IORO*
,
I1\ I
~t7- : t 5
-t1 t4
MD15-MOO
X
\ /FIGURE 4-18 Read data transfer cycle timing.
MA2-MAO
MCS(N)*
- + j < I f - - - -t 17 - - - . j
---Ir---~---MWAIT*
~~---t12---~
IOWRT*
M015-MOO _____________ t_lO ____________
~~~~.~~~~~~----t1-3~~~~~---~.-1~._tl_4~~
FIGURE 4-19 Write data transfer cycle timing.
151
152 THE MULTIBUS FAMILY OF BUS STRUCTURES
imum of 50 ns (t1O) and activates a chip select line (MCSI * or MCSO*) in a minimum of 25 ns (t7) before the IORD* signal is driven active.
If the write operation is a full-speed type of data transfer (noninterlocked), the command will remain active a minimum of 300 ns (tI2 ) and the data will be valid a minimum of 250 ns (tIS) before the IORD* is driven inactive. The iSBX Multimodule must store the data in the addressed port during this time.
If the write operation is an interlocked type of data transfer, the iSBX Mul-timodule must drive MWAIT* active (low) in less than 75 ns (tI9)' The iSBX Multimodule board must complete the write operation in less than 4 ms (tl7).
Once the data is stored in the addressed port, the MW AIT* signal is driven inactive (high). The baseboard can drive IORD* inactive (high) in a minimum of 0 ns (t25)'
In both cases, once the IORD* signal is driven inactive, the baseboard must hold the data valid for a minimum of 30 ns (tI4 ), the address for a minimum of 30 ns (tll ), and the chip select line for a minimum of 30 ns (ts).
DIRECT MEMORY ACCESS OPERATION
Timing for a DMA operation is shown in Fig. 4-20. An iSBX Multimodule ini-tiates a DMA cycle by activating its MDRQT signal. Once the DMA controller on the baseboard gains control of the baseboard's local bus, it activates MDACK*. The DMA controller must wait a minimum of 25 ns (t20) before the iSBX bus command goes active. The iSBX MUltimodule board must remove MDRQT (go inactive) in a maximum of 150 ns (t22 ) to guarantee the DMA controller will not go into burst mode. The Multimodule board can perform an interlocked or non interlocked type of data transfer. Once the data operation is complete and the command is driven inactive, the MDACK* signal must be held a minimum of 25 ns (t2I ). If the TDMA signal is used, it must be held active a minimum of 300 ns (t23)'
MDRQT~
MDACK*
10 CMD*
TDMA FROM
MULTI MODULE - - - I t l - - - + - - - - ' f - - - - J
t23--J
'----TDMA FROM
BASEBOARD _ _ _ ~:
l---
/ 4-FIGURE 4-20 DMA data transfer cycle timing.
J ----t15 ----... ·r;.----t16 --~1
MCLK ' - - - " \ , - - - , - ,_ _ _ _ FIGURE 4·21 iSBX bus Multimodule clock timing.
o V - - - ' "
> 0 ns RESET _ _ - - L
,---
_ _ ~FIGURE 4·22 Reset timing.
MISCELLANEOUS TIMING
Figure 4-21 is a diagram of the timing of the Multimodule clock (MCLK), and Fig. 4-22 is a timing diagram of initialization (RESET).