22 2. Power Amplifier Characteristics ACLR has the same definition as the ACPR but the output power is filtered through the system filter and (2.20) and (2.21) can be applied directly.
2.4 Stability problem with PA 23 The advantage of these parameters is that they can identify where the un-stability occurs, i.e.,µ for the input side andµ′ for the output side. Additionally, they tell how far the stability is from the presented impedance at the input and output terminals [24].
2.4.1 Oscillation suppression techniques
Stabilization network technique prevents the amplifier from going into the unstable region and it lowers the amplifier gain. The most common stabilization networks are shown in Fig. 2.11. For very-high gain transistors, a series resistor can be used in series with the gate, as in Fig. 2.11.a, to reduce the negative resistance and force the unstable region to be outside of the Smith chart.
However, this circuit may reduce the gain drastically. Usually, this resistance value is very small to allow reasonable gain.
Another stabilization technique is a parallelRCcircuit connected in series to the gate, Fig.
2.11.a. This circuit is similar to the previous; however, the capacitor is used to bypass the RF component in the targeted design. Thus, a capacitor with self-resonant frequency (SRF) centred on the targeted band is used to pass the wanted signal to the transistor. It is worth noting that the resistor can be high value without reducing the gain in the targeted band because it will be passed through the capacitor.
Fig.2.11.c is another technique, which suppresses the RF component which has a high gain and may cause an oscillation. This circuit is a narrow band circuit because it is used to short out the unwanted RF component. The SRF of this capacitor is chosen for the unwanted RF signal where the series resistance is very high to block the operated band to be shortened out.
The last stabilization circuit, Fig. 2.11.d, is simply the same technique as the first one in that it reduces the negative resistance. However, this resistance can be used to suppress the oscillation
R1
Q1
(a)
Rs
Cs
Q1
(b)
Rp
Cp Q1
(c)
Rp2
Lp
Q1
(d) Figure 2.11:Different stabilization techniques are used in this work.
24 2. Power Amplifier Characteristics from the DC-source. This technique is better than the one used in Fig. 2.11.a in that it does not reduce the total performance of the designed PA.
These circuits and many others can be used alone or combined to reduce the oscillation of the PA. The oscillation can be measured simply using the spectrum analyser with full sweep. Any pulses seen on the spectrum, without applying an RF signal, means an oscillation and must be suppressed using one of the four circuits shown in Fig. 2.11.
3 | Power Amplifier Operation
3.1 Load line and PA matching
As it was shown in Chapter 1, FET transistors are usually modelled as a voltage controlled current source. This source has upper and lower limits, which can be used for calculating the optimum load for PA. Considering a simple FET model as shown in Fig. 3.1, it can be seen that the minimum and maximum voltages are between 0 andVmaxand the minimum and maximum currents are between 0 andImax. If the maximum power is required from this source in highly linear operation, the voltage and current waveforms should be allowed to swing between these extreme limits symmetrically around the DC drain voltage and current. As a result, the time domain behaviour of the current waveform versus the time domain behaviour of the voltage waveform can be imposed into the I-V curve. The resulted line is called a load line and it has a slope of R1
L,opt, Fig 3.2. This load impedance (RL,opt) can be calculated using the known slope equation:
RL,opt=Vmax−0
Imax−0 = 2VDC
Imax =Vmax
2IDC =VDC
IDC (3.1)
If the load impedance is lower than the optimum load impedance,RL <RL,opt, the drain current swings between zero andImax and the drain voltage swings in the range of±ImaxRL/2 symmetrically aroundVDC. This operation is called as current clipping. On the other hand, if the load impedance is higher than the optimum load impedance,RL>RL,opt, the drain voltage varies between 0 andVmax where the drain current changes in the range of±Vmax/2RL symmetrically aroundIDC. This operation condition is known as voltage clipping.
As a conclusion, if RL =RL,opt, the transistor works with the maximum rating condition
+ Vin
−
+ Vgs
−
Id=gmVgs
+ Vds
−
Figure 3.1:Simple FET model.
26 3. Power Amplifier Operation
Ids
Vds
Imax
Vmax
IDC
VDC
1/RL,opt Q−Point
RL<RL,opt
RL>RL,opt
ImaxRL/2
ImaxRL/2 Vmax RL
2 Vmax RL
2
Figure 3.2:Characteristic I-V curve for ideal FET operation.
where the delivered power is at maximum. The output power of this case is given as:
Pout= 1
2VDCIDC =1
8VmaxImax (3.2)
The DC power delivered to the transistor is:
PDC=VDCIDC =1
4VmaxImax (3.3)
As a result the drain efficiency is given by:
η= Pout PDC = 1
2 (3.4)
This is the maximum theoretical efficiency of a Class-A power amplifier. In this class, the transistor works as a current source, conducting all the time (2π), by choosing the quiescent point to be exactly in the middle of the device current and voltage, as in Fig 3.2. It is the ideal choice for the applications that require high linearity amplifications because the drain voltage and current remain unclipped for all the input values below the 1-dB compression. However, this class has the poorest efficiency given that all the time there is overlapping between the drain voltage and current, see Fig 3.3.
Vd[V],Id[A]
ϑ[rad]
0 π/2 π 3π/4 2π
Vd Id
Figure 3.3:Class-A power amplifier waveforms