Parasitic effects on gain and power

A basic FET-model is shown in Fig. 3.22. The transistor is modelled as a voltage controlled current source with a value ofg_mV_gs(t), whereg_mis the input transconductance andV_gs(t)is the voltage at the input terminal of the transistor. The parasitics from the semiconductor layers are represented between the three terminals as capacitance. In Fig 3.22, a signal generator with input impedanceZ_in is stimulating the transistor. The output power is terminated in load impedanceZ_L. In this circuit, the input power is:

P_in= 1

2|I_in|²R{Z_in} (3.63)

− V_s+(t)

Z_s

ZL

I_in C_{gd I}

Cgd

+ V_gs(t)

-C_gs g_mV_gs(t)

I_d1

C_ds + V_ds

-I_out

Z_L

Figure 3.22:Circuit model for FET with major parasitic capacitances

44 3. Power Amplifier Operation Where the input current can be written as:

I_in=I_Cgs−I_Cgd (3.64)

with

I_Cgs= j V_gs

X_Cgs (3.65)

and

I_Cgd= jV_out−V_gs

X_Cgd (3.66)

The output voltage is then:

V_ds=V_out =I_outZ_L (3.67)

Substituting (3.66), (3.67) and (3.65) in (3.64), the resulted input current is calculated as:

I_in = j

(X_Cgs+X_Cgd X_CgdX_Cgs

)

V_gs−j Z_L

X_CgdI_out (3.68)

From (3.68) it can be seen that the input current is a function of the output voltage (Z_LI_out). The reason for this is the feedback capacitorC_gd. The output power is calculated using:

P_out= 1

2|I_out|²R{Z_out} (3.69)

where the output current is:

I_out=−I_d−I_Cgd−I_Cds=−g_mV_gs+V_out−V_gs

jX_Cgd + V_out

jX_Cds (3.70)

substituting (3.67) in (3.70) and rearranging the equation, the output current is:

I_out =

( (−g_mX_Cgd+ j)X_Cds X_CgdX_Cds+ jZ_L(X_Cgd+X_Cds)

)

V_gs=βV_gs (3.71)

Finally, by substituting (3.71) in (3.69) the output power can be rewritten as:

P_out = 1 2

⏐

⏐

⏐

⏐

(−g_mX_Cgd+j)X_Cds X_CgdX_Cds+jZ_L(X_Cgd+X_Cds)

⏐

⏐

⏐

⏐

2

|V_gs|²R{Z_out}

= 1

2|β|²|V_gs|²R{Z_out}

(3.72)

From (3.71) and (3.68), the input current can be calculated as:

I_in= j

(X_Cgs+X_Cgd−Z_LX_Cgsβ X_CgdX_Cgs

)

V_gs= jγV_gs (3.73)

3.3 Efficiency and power limitations in power amplifiers 45 Hence, the input power is:

P_in = 1 2

⏐

⏐

⏐

⏐

X_Cgs+X_Cgd−Z_LX_Cgsβ X_CgdX_Cgs

⏐

⏐

⏐

⏐

2

|V_gs|²R{Z_in}

= 1

2|γ|²|V_gs|²R{Z_out}

(3.74)

Simply the power gain can be calculated as:

G_p= P_out P_in =

⏐

⏐

⏐

⏐ β γ

⏐

⏐

⏐

⏐

2R{Z_out}

R{Z_in} (3.75)

In (3.72) and (3.75), a full capacitance parasitic influence on the output power and gain is shown respectively. The gain equation in (3.75) is shown over the frequency with different values of parasitics in Fig. 3.23. The dashed line in these figures represents the unity gain where the corresponding frequency is the maximum oscillating frequency f_max. The gain in Fig. 3.23.a for allC_gshave the same value at 2.8 GHz. This is because the load impedance, which is composed ofR_L =1ΩandL_L=2.696 nH, is equivalent toX_Cds//X_Cgd. Sweeping the gate-drain capacitor have big influence on f_max, Fig. 3.23.b. This figure shows that the gain at small frequencies is almost identical with all swept values ofC_gd. This is logically because the impedance ofC_gd at

Gain[dB]

-20 0 20 40 60

Freq [GHz]

0 2 4 6 8

Decreasing Cgs Cds=1.0 pF Cgd=0.2 pF

(a)

Gain[dB]

-20 0 20 40 60

Freq [GHz]

0 2 4 6 8

Decreasing Cgd Cgs=2.0 pF Cds=1.0 pF

(b)

Gain[dB]

-20 0 20 40 60

Freq [GHz]

0 2 4 6 8

Decreasing Cds Cgs=2.0 pF C_gd=0.2 pF

(c)

Figure 3.23: Calculated gain from (3.75) over the frequency with a)C_gsof a range between 2 pF and 10 pF in 0.2 pF steps, b)C_gdof a range between 0.1 pF and 1.3 pF in 0.3 pF steps, and c) a)C_dsof a range between 1 pF and 10 pF in 2 pF steps;gm=0.525 S,RL=1ΩandLL=2.696 nH.

46 3. Power Amplifier Operation

fmax[GHz]

0 2 4 6 8

Cxy[pF]

0 5 10 15

Cgs

C_ds

Cgd

Figure 3.24: fmaxfor different parasitic values obtained from each diagram in Fig. 3.23 crossing the unity power gain (zero in dB). For each graph in the diagram, the other capacitance values are kept similar to Fig. 3.23.

these frequencies has a large value which eliminates the feedback effect. This is also valid for sweepingC_ds, Fig. 3.23.c.

The maximum frequency (f_max) is shown in Fig. 3.24, which are calculated from Fig. 3.23. It is shown that theC_gd has a major influence on f_maxbecause it presents the effects of the output capacitance (C_ds) on f_max.

The output power and gain equations require a tedious calculation and simplification to represent a useful meaning. In the following sections, an individual influence fromC_gsandC_ds will be presented and discussed in terms of power, gain and efficiency.

3.3.2.1 C_gs influence on power, gain and efficiency

Solving the limit ofβandγin (3.71) and in (3.73), forC_dsandC_gd approaching zero will result inβ_Cgs andγ_Cgsas:

XCdslim→∞ lim

XCgd→∞β=β_Cgs=−g_m (3.76)

X_Cdslim→∞ lim

X_Cgd→∞γ=γCgs=−j 1

X_Cgs =ωC_gs (3.77)

Substituting (3.76) and (3.77) in (3.72) and in (3.75), the output power and gain are:

P_out= 1

2g²_m|V_gs|²R{Z_out} (3.78) G_p= g²_m

ω²C_gs²

R{Z_out}

R{Z_in} (3.79)

3.3 Efficiency and power limitations in power amplifiers 47 To calculate the drain efficiency, the dissipated power must first be found. The dissipated power can be calculated from (3.78) and (3.61):

P_diss = P_diss,ideal+P_out,opt−P_out,lossy

= 1

2P_DC+1

2g²_m|V_gs|²R{Z_out,opt}

− 1

2g²_m|V_gs|²R{Z_out,lossy} (3.80) In (3.80)Z_out,opt andZ_out,lossyare the optimum load impedance without knee voltage and parasitic effect and the load impedance with knee voltage and parasitic effect, respectively.Z_out,optis given by (3.1). On the other hand,Z_out,lossywith the presence ofC_gsand knee voltage is given in (3.55).

Thus, (3.80) reduces to:

P_diss = 1

2P_DC+1

2g²_m|V_gs|²1 2

V_DC I_DC[V_knee

V_DC ]

= 1

2P_DC+P_out,opt[V_knee

V_DC ] (3.81)

The efficiency is then:

η= 1

2(1−V_knee

V_DC ) (3.82)

This result is expected because (C_gs has no effect on the efficiency and power as discussed before. This result concludes thatC_gs does not have influence on the output power and efficiency.

However,C_gs is important to give a finite gain. On the contrary, for very low frequencies the gain is very high, which is a major reason to make the transistor oscillate on these frequencies.

Usually, the stability circuit is designed at the gate side to reduce this gain. In the next section C_gs will always be present in the analysis.

3.3.2.2 C_dsinfluence on power, gain and efficiency

AssumingC_gd is zero and solvingβandγyieldingβ_Cdsandγ_Cds:

XCgdlim→∞β=β_Cds= −g_mX_Cds

X_Cds+jZ_L (3.83)

XCgdlim→∞γ=γ_Cds=−j 1

X_Cgs =−jωC_gs (3.84)

As a result, the output power and the gain can be obtained as:

P_out = 1 2

⏐

⏐

⏐

⏐

g_mX_Cds X_Cds+jZ_L

⏐

⏐

⏐

⏐

2

|V_gs|²R{Z_out} (3.85)

48 3. Power Amplifier Operation

G_p=

⏐

⏐

⏐

⏐

g_mX_CdsX_Cgs X_Cds+ jZ_L

⏐

⏐

⏐

⏐

2R{Z_out}

R{Z_in} (3.86)

It can be easily seen that the maximum power will be reached, in an ideal case, whenC_dsis zero, which will give the same result as in (3.56). Another possible maximum is when the imaginary impedance part in the load is equal to the conjugate of the impedance inC_ds. The latter case is called a conjugate match, where the output power and, hence, the gain are:

P_out =1 2

1 R{Z_out}

g²_m

ω²C_ds² |V_gs|² (3.87)

G_p= 1

R{Z_out}R{Z_in} g²_m

ω⁴C_ds²C_gs² (3.88)

In this case, the output power and gain are reduced from the optimum case in (3.78) by a factor of(X_Cds/R{Z_out})². This factor is equal to the square of quality factorQ, which represents the switching loss of theC_ds. Due to the large output capacitance in the FET transistor(C_ds), the accounted loss, in addition to the operating frequency, are the major limiting factors on efficiency and power.

The dissipated power for a Class-A power amplifier with all parasitics, includingC_ds, and knee voltage is equal to:

P_diss= 1

2P_DC+P_out,opt[1−ξ(1−V_knee

V_DC )] (3.89)

where

ξ_Cds=|β_Cds|²= X_Cds²

|Z_L−jX_Cds|² (3.90)

The efficiency is then:

η= 1

2ξ_Cds(1−V_knee

V_DC ) (3.91)

There are two cases for the efficiency presented in (3.91) C_ds=0⇒ξ=1 and hence the efficiency reduces to (3.58)

C_ds̸=0: In this case, usually the load impedance is designed to get the maximum output power from the transistor. According to (3.85), the output impedance should absorb the output capacit-ance, i.e.;Im{Z_L}=X_Cds. Hence,

ξ_{Cds_opt}= 1

ω²C_ds² Re{Z_L}² (3.92)

and the efficiency is:

η= 1 2

1

ω²C²_dsRe{Z_L}²(1−V_knee

V_DC ) (3.93)

3.3 Efficiency and power limitations in power amplifiers 49 where

Re{Z_L}=R_Lopt,lossy= 1

2(V_DC−V_knee

I_DC ) (3.94)

As it was shown before, the switching loss due toC_dslimits the efficiency of the power amplifier.

In addition, the efficiency decreases as the frequency increases, which makes highly efficient power amplifier designs at high frequencies a real challenge.

3.3.2.3 C_gd influence on power, gain and efficiency

Similarly,βandγwith presence ofC_gd andC_gsonly is given byβ_Cgd andγ_Cgd:

XCdslim→∞β=β_Cgd=−g_mX_Cgd+j

X_Cgd+jZL (3.95)

X_Cdslim→∞γ=γ_Cgd= X_Cgs+X_Cgd−Z_LX_Cgsβ_Cgd

X_CgdX_Cgs (3.96)

P_out =1 2

⏐

⏐

⏐

⏐

g_mX_Cgd−j X_Cgd+jZ_L

⏐

⏐

⏐

⏐

2

|V_gs|²R{Z_out} (3.97)

G_p=

⏐

⏐

⏐

⏐ β_Cgd γ_Cgd

⏐

⏐

⏐

⏐

2R{Z_out}

R{Z_in} (3.98)

The efficiency is similar to (3.91) with:

ξ_Cgd=|β_Cgd|²=

⏐

⏐

⏐

⏐

⏐

X_Cgd−_g^j

m

Z_L−jX_Cgd

⏐

⏐

⏐

⏐

⏐

2

(3.99) There are two cases to be considered for the efficiency:

C_gd=0⇒ξ=1 and hence the efficiency reduces to (3.58)

C_gd ̸=0: In this case, obtaining the maximum power from the transistor requires the load imped-ance to absorb the output capacitimped-ance (3.97), i.e.;Im{Z_L}=X_Cds. Hence,

ξ_{Cgd_opt} = g²_m+ω²C_gd²

g²_mω²C_gd² Re{Z_L}² (3.100) WhereRe{Z_L} is given similar to (3.94) in addition to the switching loss due toC_gd and the operating frequency, the input transconductance limits the efficiency of the power amplifier as concluded in (3.100).

50 3. Power Amplifier Operation 3.3.2.4 C_dsandC_gd influence on the efficiency

If all major analysis and knee voltages affect the dissipated power (3.62), the efficiency will be given as in (3.91). However,ξwill change to take both capacitances in effect as:

ξ=

⏐

⏐

⏐

⏐

⏐

(X_Cgd−_g^j

m)X_Cds X_CgdX_Cds+jZ_L(X_Cgd+X_Cds)

⏐

⏐

⏐

⏐

⏐

2

(3.101) Ideally, the load impedance should absorb the output parasitics of the transistor to get high output power and efficiency. In this caseX_L is equal to|X_Cds//X_Cgd|. Hence, (3.101) will be:

ξopt= 1 g²_m

⏐

⏐

⏐

⏐

(g_mX_Cgd−j)X_Cds Re{Z_L}

⏐

⏐

⏐

⏐

2

= 1 g²_m

(g²_m−ω²C_gd² )

ω⁴C_ds²C_gd² Re{Z_L}² (3.102) From (3.102), efficiency of power amplifier changes with transconductance of the FET due to the feedback capacitance between the output and the input terminals of the FET (C_gd). On the other hand, the efficiency here decreases rapidly with frequency due to the two frequency dependent impedances|X_Cds//X_Cgd|.

The drain efficiency factor is shown over the frequency with sweeping C_gd and C_ds in Fig. 3.25.a and Fig. 3.25.b, respectively. From these figures, it is worth noting that the efficiency factor is only valid if it is below one. However, the graph in Fig. 3.25 gives an overview of parasitic influence on the drain efficiency.

All these analysis are made by assuming a linear capacitance model. However, very complic-ated equations can be obtained if the dependent voltage relation of the parasitics (g_m,C_gs,C_ds andC_gd) is substituted in the previous analysis.

ξ

0 0.2 0.4 0.6 0.8 1

Freq [GHz]

0 2 4 6 8

Decreasing Cgd Cds=1.0 pF

(a)

ξ

0 0.2 0.4 0.6 0.8 1

Freq [GHz]

0 2 4 6 8

Decreasing Cds Cgd=0.2 pF

(b)

Figure 3.25:Calculated efficiency factor from (3.102) over the frequency with a)C_gd of a range between 0.1 pF and 1.3 pF in 0.3 pF steps, and b)C_ds of a range between 1 pF and 10 pF in 2 pF steps;g_m=0.525 S,R_L=1Ωand L_L=2.696 nH.

4 | Single Band Power Amplifiers

To investigate highly efficient broadband power amplifiers, narrow band amplifiers with very high efficiency are designed and analysed. In this chapter, these amplifiers are discussed in terms of design, efficiency, power capability and broadband operation. The power amplifiers are based on [Paper D] and [Paper E].

The first section will present an inverse Class-D power amplifier. The design technique and its result are shown. In the second section, an inverse Class-F power amplifier is presented with a novel matching network integrated with the required resonator. Finally, the last section will discuss power amplifier classes capabilities for broadband applications based on theoretical analysis.

4.1 Inverse Class-D PA

The various Class-D power amplifiers, as discussed previously, have different advantages. For instance, VMCD PA operate on lower peak voltage (V_d,max =2V_dd). On the other hand, CMCD-PA have very high peak drain voltage (V_d,max=πV_dd). This might make the transistor exceed the breakdown region and, hence, cause transistor damage. However, for current transistor technology e.g., GaN HEMT, peak drain voltage has minimal concerns in PA design.

Inverse Class-D PA might include the output capacitance of the transistor in the main resonator.

As a result, low switching loss is achieved. This makes inverse Class-D more preferable for high frequency power amplifiers.

Im Dokument Bandwidth considerations of high efficiency microwave power amplifiers (Seite 73-81)