Readout electronics

6.1.1 Overview

A minimum ionizing particle (mip) passing a GEM-MSGC produces about 27 electrons in the active detector volume (drift gap). They will be amplified in the GEM and at the anodes to a pulse of about 110’000 electrons at a gas gain of 4000 (see Section 3.3). In first order the length of the pulse is defined by the drift velocity and the size of the drift gap. A drift velocity of about 7.5 cm/µs (Ar/CO₂ 70/30 at 5 kV/cm [50]), and a drift gap of 3 mm results in a typical pulse length of 40 ns. This charge is collected, integrated, amplified and stored in the Helix readout chip.

6.1 Readout electronics 67

The HERA-B experiment requires a dead time free readout system in contrast to most earlier experiments in which further events were ignored until the whole event is read out after receiving a trigger. At HERA-B the data are temporarily stored in pipelines.

After receiving a trigger the appropriate event is read out of the pipeline. However, further events are still written into the pipeline during the readout.

To economize developing time and manpower, a common readout system for the vertex detector and for the inner tracker was designed. The same readout chips are also used in the HERA-B and ZEUS vertex detector [51].

Figure 6.1: The readout electronics chain at HERA-B (from [38])

Figure6.1gives a short overview over the HERA-B readout system. 128 anodes (the sixth part of a whole MSGC) are connected to one Helix readout chip. In a first step the MSGC signals are preamplified and shaped in the Helix chip. These shaped signals are tem-porarily stored in the pipeline. Additionally they are discriminated to gain a fast trigger signal. Every input channel with a signal above an adjustable threshold generates a dig-ital trigger signal. Four adjacent channels are combined by a logical OR and transferred to the HERA-B level 1 trigger logic.

The analog signals are transmitted optically to the FED board (Front End Driver) in the electronics hut where they are digitized. The digitized data are stored in the second level buffer (SLB) consisting of Sharc digital signal processors. At the HERA-B experiment they take the second level trigger decision. Accepted events are transferred via Sharc-Links from the Sharc boards to the Linux processing farm to take the third level trigger decision. At the PSI tests the digitized data of every triggered event are read out of the Sharc boards by a Cetia VME-CPU and copied via Ethernet to disk there is no second level trigger.

6.1.2 The Helix readout chip

The Helix readout chip was designed at the ASIC laboratory Heidelberg for the special requirements of the vertex detectors at HERA-B and Zeus as well as for the inner tracker

at HERA-B. Its main characteristic are [52]:

• 128 channels with a pitch of 50µm, given by the pitch of the silicon microstrips.

• A charge sensitive preamplifier for positive and negative pulses.

• A pulse shaper creates a semi Gaussian pulse with a rise time adjustable between 30 ns and 70 ns. That means, that the rising edge has a Gaussian shape and the pulse decays somehow exponentially.

• A comparator for each channel delivering a logical trigger signal if the pulse is higher than a given threshold. Four adjacent channels are combined by a logical OR.

• An analog pipeline for each channel consisting of 141 cells.

• A charge sensitive pipeline readout amplifier.

• A multiplexer to switch the 128 channels to one output channel.

• A current driver at the output.

FcsTp Tp Idriver Vfp Vfs

Vfp

Figure 6.2:Diagram of the Helix readout chip (from [52])

The electrical properties of the amplifiers, shapers, current buffers and comparators can be adjusted by control voltages and currents respectively originating in the bias gener-ator. The integration time, noise characteristics, pulse shape and amplification can be programmed in this way. Even radiation damages of the Helix readout chip can be com-pensated to a certain amount.

6.1 Readout electronics 69

The analog memory of the Helix chip consists of a capacitor array, 128 channels by 141 columns. The actual pipeline is 128 cells long, i.e. after 128 bunch crossings an event is overwritten by a new one. Triggered events are marked to prevent them from being overwritten until they are read out. A maximum of eight events can be marked, they form the multievent buffer. The five additional cells are needed for the internal organization of the pipeline. This adds up to 141 (128+₈+5) columns. Small production differences of the capacitors, preamplifiers and shapers (each channel has its own preamplifier and shaper) lead to different offsets. This has to be corrected in the data (see Section6.3).

For proper operation the Helix chip needs various control signals. The Hera clock (BxClk

= bunch crossing clock) ensures that it is running synchronously to the Hera machine.

Within the Helix chip it is called sampling clock (SClk). On the falling slope of theSClk the preshaped signals are sampled and stored in the pipeline. The readout of a stored event is initiated by aTriggersignal. The readout frequency (RClk) can be asynchronous to the signal sampling, 10 MHz, 20 MHz or at a maximum rate of 40 MHz.

The signal TestPulse stimulates the Helix chip to write a test pattern into the pipeline, which afterwards can be read out. It is a stair like pattern: a pulse of +2 Mip_Si (1 Mip_Si corresponds to 24 000 e⁻ [52]) is written into the first channel, +1 Mip_Si, -1 Mip_Si, and -2 Mip_Siinto the succeeding channels. For the remaining channels this pattern is repeated.

This allows us to check the readout chain from the Helix chip to the computer. A Reset pulse at the beginning of a new run ensures that every Helix chip starts storing the events in the first pipeline column. These five control signals are all produced by the FED con-troller.

6.1.3 The readout chain

Two Helix chips are packed together onto one printed circuit board (PCB) (AS7). Three of these Helix chip PCBs are bonded to one chamber using Kapton foils. The fan-ins are equipped with a 600Ωresistor to protect the Helix chip from high input currents, triggered by anode shorts or discharges.

The signal distribution board (AS15) reads out the six Helix chips, always two in a series, i.e. one after the other, in the so-calleddaisy chainmode. On theAS15board the signals are amplified and afterwards transmitted differentially to the analog–optical transmitter.

The signals attain the electronics hut over an optical fiber. This prevents noise induction over the transmission line and decouples the chamber electronics from the electronics in the electronics hut.

The analog data is digitized in the FED board with an 8-bit ADC (analog to digital con-verter) and stored as data blocks including the FCS data (fast control system) in the header and trailer in the SLB (second level buffer = Sharc board). Finally, the data is read out by a Cetia PowerPC CPU and transferred over Ethernet to disk.

SClkRClk TrigIn Reset Testpulse

CAN BUS

Sharc Board FED Contoller FED Repeater FED Switch FED Board

Cetia CPU Distribution BoardAS15 Signal

PCB AS7

IF7 Data Valid Modul Opt. Electrical IF9 Opt. Dig. Trans

CAN Bus

lower VME Bus

IF1 Opt. Analog

Opt. Dig. Receiver

Sharc Cable

Figure 6.3: The readout electronics: The Helix chip PCBs and the signal distribution board AS 15 are mounted next to the chambers. The optical transmitter and receiver (IF1 and IF6-1) were placed about 1.5 m underneath the chambers in the experimental area. The whole rest resides in the electronics hut.

6.1.4 The controlling electronics

The Cetia CPU additionally controls the whole VME crate. It initializes the FED con-troller, and writes the programmable parameter of the Helix chip over the CAN bus into the chip. At HERA-B the CAN bus is the standard way to distribute new settings and to collect slow control data (like temperatures or measured currents). During the PSI tests we only use it to program the Helix chips.

The FED controller generates the needed digital (timing) signals likeSClk,RClk,TestPulse