SECTION 3 THEORY OF OPERATION
31 RAEN- RAEN-32 VPS1+
33 VPS2+
34
ROEN-35
NLEN-36
VPST-37 RRTO+
38 BRT1+
39 BRT2+
NOTE: Branch
Write (low
=
write, high=
read;FTCH- bit must be low).Data available (loads output data register for 1/0 transfers).
Select display parameter register (for display processor read display parameter register).
Next instruction (low true in last step of each instruc-tion; loads address counter with start address of next instruction).
Graphic controller request enable (low when graphic controller halted).
Function generator busy enable (causes wait if a function generator is busy).
Radar branch test (radar capabiU.ty expansion bit).
Vector position start 1 (vector position information bit to ramp generator).
Vector position start 2 (vector position information bit to ramp generator).
Rotate enable (causes Y axis incrementing for rotated charaeters).
Null enable (disables tab moves if NULL- from character generator is low true) •
Vector position start (start instruction to ramp gen.erator).
Branch test bit O.
Branch test bit 1.
Branch test bit 2.
conditions estaplished by BRTO through BRT2 as follows:
(
BRT2+ BRTI+ BRTO+ BRANCH CONDITION
L L L Absolute (unconditional)
L L H TOGL flip-flop (conditional branch)
L H L Not used
L H H PHOTOPEN enabled (conditional branch)
H L L Zero detect (conditional branch)
H L H Indirect bit (conditional branch)
H H L Radar request (conditional branch)
H H H Branch inhibit
Timing and Miscellaneous Logic. This circuit provides timing signals to coordi-nate the operation of all graphic controller circuits. The timing signals are de-rived from the CLOK-F (master clock) input from the ROM and status logic. CLOK-F is normally a IO-MHz signal generated by the ROM and status logic, but an optional external clock signal may be used.
The timing and miscellaneous logic accepts control inputs from other terminal controller cards. These input signals include: REST-B (bus reset) from the display processor; PPDT-F (PHOTOPEN detect interrupt) from the ROM and status logic; SYNC-O
(frame sync) from the output channel, and FBSY- (function busy) from any of several cards connected to the graphic bus. Each signal modifies the timing and miscella-. , neous logic outputs as required to coordinate graphic controller operations with the operations performed by other cards. Auxiliary inputs are also provided to accommo-date systems configured to operate with various external equipments.
A third timing and miscellaneous logic function is to monitor and generate processor bus status signals; i.e., BUSB-B (bus busy), WRIT-B (write), ADRV-B
(address valid), MEMA-B (memory acknowledge), and GRAI+ (grant input). Except for GRAI+, each signal can be either an output (when the graphic controller controls the bus) or an input (when another device controls the bus). GRAI+ is an input signal only, and is .generated by the ROM and status logic to indicate that the graphic controller may control the bus (high GRAI+) or that another device controls the bus
(low GRAI+). Note that, in a standard terminal controller configuration, the graphic controller position gives i t the lowest priority with regard to being able to assume processor bus control.
Two addition"al signals generated by the timing and miscellaneous logic are BYTE-G (byte) and GCRE- (graphic controller request enable), which are sent to the ROM and status logic. The BYTE-G signal goes low to indicate a byte operation is being performed by the graphic controller; and is high to indicate a word operation is being performed. GCRE- indicates when the graphic controller is running (GCRE-high) or when the graphic controller is halted (GCRE- low). As a maintenance aid,
the complement of GCRE- (GCRE+G) is monitored by LED indicators DSIO (marked RUN) on the graphic controller card and DS2 (marked DISPLAY) on the terminal controller front panel assembly. These indicators light when the graphic controller is running and go out when the graphic controller is halted.
3-87
•
!
I
Function Decode Logic. This circuit decodes function select signals generated by the control ROM in the control logic (function select signals correspond to the microcontroller B address signals listed in table 3-26). The resulting function control signals are then distributed as required to circuit cards to produce the display image. Specific signals generated by the function decode logic and their destinations are shown in figure 3-18.
3-88
Table 3-26. Graphic Controller Microcontroller Register Addresses and Function Control Signal Selection Codes
B ADDRESS BIT MICROCONTROLLER FUNCTION
B3
I
B2I
B1I
BO REGISTER CONTROL SIGNAL'a a 0 0 DRa
HALT-a a a 1 DR1
LDIR-a a 1 a DR2
FRDY-a a 1 1 DR3 DRDY-,
a 1 a a Dwa
LINK-a 1 a 1 DW1
VPIZ-a 1 1 a DSP
WAlT-a 1 1 1 DPC
LDMA-1 a 0 a DTI
STRT-1 a 0 1 DPR
STDP-1 0 1 0 DZR
STDZ-1 0 1 1 DCR
STDC-1 1 0 0 DYR
STDY-1 1 0 1 DXR
STDX-1 1 1 a KYR
STKY-1 1 1 1 KXR
STKX-NOTE: Function control signals are generated only when the FGEN-(control ROM bit 18) signal is low true.
(
"I
·
I
I
,
:
,
:
·
·
I
( / ,
I
(~
3.9.2 OPERATION. When refreshing, the graphic controller requests and gains control of the graphic bus. The display program counter contains the address of the next instruction in the refresh memory. The next instruction can be loaded into the instruction register as soon as the previous instruction data has been used. This enables fetching and loading the next instruction while the function generator is busy. This process of fetching and executing instructions continues until a wait control bus command occurs. The,next frame sync pulse restarts the refresh process.
The execution of an instruction is as follows: The nine operation code bits in the instruction are used by the refresh instruction decoder to point to the starting address for each microinstruction routine in the control ROM. At the start of the execution, this starting address is loaded into the ROM address counter. The address counter is normally incremented by the sequence control and sequences through the steps required for the instruction. The address counter is -loaded instead if condi-tional or absolute branching is microprogrammed so as to repeat a sequence or to jump to a different sequence. The address counter is normally incremented every 300 ns, but the cycle time can be delayed if the micro step enables it by gating off the clock with a wait-if-busy condition. The last word of a refresh instruction has a "next instruction" bit which forces the address counter to be loaded with the starting address of the next instruction sequence.
The execution of certain instructions requires sign extending or byte swapping.
The appropriate micro steps of the instruction contain ROM bits which control the byte and sign extend multiplexer so that the current data is entered into the micro-controller. All micro steps for a given instruction are executed sequentially unless one of,the following conditions occur when enabled: branch absolute, branch if in-direct, branch if zero, branch if PHOTOPEN enabled, and branch if radar request. The eight LSBs of the branch address, which are programmed in the control ROM, go to the address counter when enabled through the address multiplexer. The address counter MSB remains unchanged after conditional branching, while absolute branching sets the MSB. Absolute branching, therefore, can on;I.y be done to the upper 256 locations of the 512 x 40-bit control ROM.
The functions "rotate" and "null" are performed external to the microcontroller.
An enabled'''rotate'' status forces the LSB of the micro controller B register select to true so that the DY register is modified by the text increment instead of the DX register. The "null" indication, from the character generator, disables the text increment function. The microcontroller instruction is modified so that the text increment data is not added to the X (or Y) position register. The vector start, to the vector position generator, is also disabled.
If the graphic controller is stopped while executing a graphic instruction, the address counter resets when the current instruction is completed. The address multi-plexer is disabled so that the stop, rather than the next starting, address is loaded into the address counter.
The graphic controller can be stopped by a function command from the display processor, by a halt or link refresh command, or by a PHOTOPEN strike. While at the stop address, the graphic controller enables and waits for a read or write register command or a continue function command from the display processor. The control instruction decoder is enabled and, through the address multiplexer, points to the starting of the appropriate micro routine.
3-89
The address decoder provides four address bits and the read/write line to the control instruction decoder. The control instruction decoder (as well as the refresh instruction decoder) provides the eight LSBs to the address multiplexer. The MSB i's zero so that all I/O and refresh instructions start in the lower 256 locations of the control ROM. An absolute branch to the upper half allows the entire ROM to be used for instruction microprogramming.
The display processor reading a graphic register causes a return to the stop address when the read is completed. If a function command continues or a write display program counter is performed, the graphic controller resumes executing refresh instructions. (NOTE: The graphic registers are all contained in the micro-controller which provides the read register data.)
3-90