SECTION 3 THEORY OF OPERATION
3.9 GRAPHIC CONTROLLER
The primary functions of the graphic controller are to retrieve the display instructions from refresh memory; extract, reformat, calculate, and distribute the data contained in these instructions; and initiate the actions required by the
instructions. The instruction set is described in', the programmer's reference manuals listed in Appendix C.
The graphic controller maintains the instruction address, controls instruction memory fetches, and performs any branching specified by control (non-graphic)
instructions.
The graphic controller also initiates the operations required to execute the draws and moves specified by the graphic instructions. Each graphic instruction con-sists of an operation code, which specifies the action :required, and the data which is to be distributed. The graphic instructions require the distribution (loading) of the data into a data register located in the graphic controller, the vector/
pOSition generator, the character generator, the output channel, or the optional conics generator. A move instruction requires the additional step of moving the beam, blanked, to the position indicated by the data. A draw instruction is a move instruction with the beam unblanked.
The graphic controller (figure 3-18) contains logic circuits that can be grouped into six functional areas: input/output logic, instruction logic~ control logic, central processing logic, function decode logic, and timing and miscellaneous logic.
These circuits operate together to (a) process display instructions contained in re-fresh files and (b) control the image-generating circuits on other circuit cards.
These circuits are described in the following paragraphs.
3.9.1 MAJOR CIRCUITS
Input/Output Logic. This circuit handles all informat,ion sent to or 'from the graphic controller via data bus lines (DAnn-B) or address bus lines (ADnn-B) on the processor bus. The I/O logic contains three registers and a read-only memory (ROM) for this purpose.
Input information handled by the I/O logic comprises (a) graphic controller input data and instructions received 'Via the data bus lines and (b) register
addresses received via the address bus lines. Input data and instructions are loaded into an instruction register and applied to the instruction logic. Register addresses go to a ROM which decodes the addresses and sends signals to the control logic to initiate a read/write operation as required.
Output information handled by the I/O logic comprises (a) data applied to the processor bus data bus lines and (b) refresh file addresses applied to the processor bus address lines. Both types of output information come to the I/O logic from the central processing logic. Data passed via the I/O logic are graphic controller register data generated in response to a display processor register read command.
These data are applied to the data bus lines via an output data register in the I/O logic. The output addresses placed on the address bus lines are memory locations containing the refresh file (display instructions) to be processed by the graphic controller. These addresses are generated by the central processing logic and applied to the address bus lines via a display program counter register in the I/O logic.
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Instruction Logic. This circuit accepts instructioninformat,ion from the instruction register in the I/O logic and decodes the information to initiate the
required action. The OP code portion of each instruction is decoded to determine ( ,I the starting location of the microroutine that executes the instruction. The start""",
ing location is applied to the control logic. If the decoded instruction contains data, the data are separated from the instruction and sent 'to the central processing
logic. '
Control Logic. This circuit determines the microroutines required to execute each graphic c()Otroller instruction. This is accomplished via a control program in the 512-by-40-bit ROM contained in the control 10glLc. The starting location of each microroutine is selected by input signals from the instruction logic. A contrOl logic counter then sequences through the remaining ROM addresses of the microroutine.
Microroutinesare also used ,to execute register read/write operations in response to display processor commands. When a register read/write operation is required, the register address is decoded by a ROM in the
r/o
logic which determines the microroutine to be used. The starting location of nhe microroutine is then applied to the control logic to initiate execution of the microroutine. A control logic,counter then sequences through the remaining addresses of the microroutine~As each ROM control program address is accessed during execution of a routine, the control ROM generates a set of 40 output signals, consisting of micro-instructions, display function select signals, and function control signals (see table 3-25). Microinstructions go to the central processing logic; the display
function select signals go to the function decode logic; and function control signals go to the ramp gen~rator, character generator, ,and output channel to control their
display functions. '
The control logic also receives external control signals: NULL-C (null) from the character generator, PPDE-F (PROTOPEN delay enable) from the ROM and status logic, and TOGL-E (toggle) from the ramp generator. NULL-C prevents a text incre-ment operation from being performed when a null charact:er is drawn by the character generat,or; PPDE-F enables a microroutine branch condition for PROTOE'EN operations;
and TOGL-E permits the state of the ramp generator toggle flip...;f1op to be sensed and retained as necessary to acconnnodate special system operating conditions (e.g., using the display indicator to display both graphics and radar illlages).
As a maintenance aid, nine LED~ (D81 through D89), indicate the states of the ROM address input at all times.
Central Processing Logic. This circuit, which contains a 16-bit microcontroller, processes data within the graphic controller. The processing microinstructions are applied to the central proceSSing logic from the control logic. 'Data to be processed comes from the instruction logic.
Central processing logic outputs include addresses and data. Addresses go to the I/O logic DPe register to select graphic controller instructions from the refresh file. Data are applied to the processor bus or the graphic bus by the applicable microroutine as required. When a register read operation is performed, data are gen-erated by the central processing logic and sent to the processor bus data bus lines
(DAnn-B) via the output data register in the I/O logic. When a display instruction
(
-, - /
is executedt the resulting data are placed directly on the graphic bus lines (DBnn-G) {- , by the central processing logic.
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Table 3-25. Graphic Controller Control ROM Bit Assignments
BIT MNEMONIC DESCRIPTION
2 12
Microcontroller microinstruction code.
Microcontroller A address bit 0; shift data override;
absolute branch address bit O.
9 Al ! Microcontroller A address bit 1; branch address bit 1.
10 A2 Microcontroller A address bit 2; branch address bit 2.
11 A3 Microcontroller A address bit 3; branch address bit 3.
12 BO Microcontroller B address bit 0; function decoder bit O.
13 Bl Microcontroller B address bit 1; function decoder bit 1.
14 B2 Microcontroller B address bit 2·
,
function decoder bit 2.15 B3 Microcontroller B address bit 3; function decoder bit 3.
16 Microcontroller carry input.
17 Memory busy enable (causes wait if memory is busy).
18 FGEN- Function generator enable (enables function decoder).
19 SREL- Short relative sign extension; branch :address bit 4.
20 TINC- Text increment sign extension; branch address bit 5.
21 RELA- Relative sign extension; branch address bit 6.
22 LBYT- Left byte select, branch address bit 7.
23 POST- Position sign extension; branch address bit 8.
24 FTCH- Fetch (initiates memory fetch).
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Table 3-25. Graphic Controller Control ROM Bit Assignments (Cont)
BIT MNEMONIC DESCRIPTION
25 WRIT-26
DAVL-27