When power is turned on, the PIa comes up in the input mode with all interrupts disabled and inhibited and control signals deactivated (low). The steps in initializing a PIa port are
. Select the operating mode by writing the appropriate control byte into the mode control register. Interrupt control as well as I/O mode information may have to be sent.
. If in mode 3, establish the directions of the 1/ a pins by writing a control byte into the input/ output control register. This byte must follow the control byte that selected mode 3.
Examples
1. Make port B output.
LD A,OOOOll11B OUT (PIOCRB),A
;MAKE PORT B OUTPUT
Bits 0 through 3 of the control byte are all I 's to address the mode control register. Bits 6 and 7 are both O's to put the port in the output mode. Bits 4 and 5 are not used.
2. Make port A input.
LD A,01001111B OUT (PIOCRA>, A
;MAKE PORT A INPUT Bit 7
=
0 and bit 6=
I to put the port in the input mode.3. Make port A bidirectional.
LD A,10001111B OUT (PIOCRA),A
;MAKE PORT A BIDIRECTIONAL
Bit 7
=
I and bit 6=
0 to put the port in the bidirectional mode. Remember that only port A can be operated in the bidirectional mode, and that port B must then be operated in the control mode.4. Make port A control with all lines inputs.
LD A,l1001111B ;MAKE PORT A CONTROL OUT (PIOCRA},A
LD A,l1111111B ;ALL BITS INPUTS OUT (PIOCRA),A
The first OUT instruction puts port A in the control mode, since bits 6 and 7 are both 1. The second OUT operation to the same address loads a different register (the
64
Z80 ASSEMBLY LANGUAGE SUBROUTINESinputj output control register). A 0 in a bit position of that register makes the corresponding pin an output, while a 1 makes it an input. The polarity here is arbitrary, and many bidirectional devices use the opposite convention.
5. Make port B control with all lines outputs.
LD A,11001111B ;MAKE PORT B CONTROL OUT (PIOCRB),A
SUB A ; ALL B ITS OUTPUTS
OUT (PIOCRB),A
The second byte is directed automatically to the inputj output control register if the first byte puts the port in the control mode.
6. Make port A control with lines 1, 5, and 6 inputs and lines 0, 2, 3,4, and 7 outputs.
LD A,11001111B OUT (PIOCRA),A LD A,01100010B
;MAKE PORT A CONTROL
;1,5,6 IN--O,2,3,4,7 OUT
INTERRUPT SERVICE ROUTINES
More information on material in this section can be found in the book Practical Microcomputer Programming: The Z80 by
w.J.
Weller, Chapter 16.Z80 interrupt systems may operate in any of three modes.ls In all three modes, the processor responds to an interrupt by executing a CALL or RST instruction which transfers control to a specific memory address and saves the current program counter at the top of the stack. Table 1-12 lists the destination addresses for the RST instruc-tions and the non-maskable interrupt. No other registers (besides the program coun-ter) are saved automatically.
There are two common approaches to saving registers:
. If there is only a single level of interrupts, primary registers may be saved in the alternate set. The service routine begins with
EX AF, AF'" ; SAVE PRIMARY REGISTERS IN ALTERNATES EXX
The EXX instruction exchanges registers B, C, D, E, H, and L with their primed equivalents. The service routine must end by restoring the original primary registers with
EXX ;RESTORE ORIGINAL PRIMARY REGISTERS
EX AF ,AF"
This approach assumes that the alternate (primed) registers are reserved for use in interrupt service routines.
CHAPTER 1. GENERAL PROGRAMMING METHODS
65
Table 1·12. Destination Addresses for RST (Restart) Instructions and the Non-Maskable Interrupt
Destination Address RST Instruction Operation Code
(Mnemonic) (Hex)
(Hex) (Decimal)
RSTO C7 0000 0
RST8 CF 0008 08
RSTIOH D7 0010 16
RST 18H DF 0018 24
RST 20H E7 0020 32
RST 28H EF 0028 40
RST 30H F7 0030 48
RST 38H FF 0038 56
Non-maskable 0066 102
interrupt
. If there are several levels of interrupts, each service routine must save all registers that it uses in the stack. Since the Z80 has so many registers, most programmers keep their service routines simple so that they must save only a few registers. Otherwise, the overhead involved in servicing interrupts (sometimes called the interrupt latency) becomes excessive. A typical sequence for saving the primary registers in the stack is
PUSH AF PUSH BC PUSH DE PUSH HL
;SAVE REGISTERS
The opposite sequence restores the primary registers.
POP HL POP DE POP BC POP AF
;RESTORE REGISTERS
Interrupts must be reenabled explicitly with EI immediately before the RET instruc-tion that terminates the service routine. The EI instrucinstruc-tion delays the actual enabling of interrupts for one instruction cycle to avoid unnecessary stacking of return ad-dresses (that is, an RET instruction can remove the return address from the stack before a pending interrupt is recognized).
You must be careful to save any write-only registers that may have to be restored at the end of the routine. For example, the PIa's control registers are all write-only, and
66
Z80 ASSEMBLY LANGUAGE SUBROUTINESmany external priority registers are also write-only. Copies of such registers must be saved in RAM and restored from the stack. A typical example is
PUSH AF
The restoration procedure must recover the previous priority as well as the original contents ofthe registers.
;RESTORE OLD PRIORITY
;PLACE IT IN EXTERNAL PRIORITY REGISTER
;SAVE COPY OF PRIORITY IN RAM
;RESTORE REGISTERS
To achieve general reentrancy, the stack must be used for all temporary storage beyond that provided by the registers. As noted in the discussion of parameter passing, space is assigned on the stack (NPARAM bytes) with the sequence
LD HL,-NPARAM ADD HL,SP LD SP,HL
;ASSIGN NPARAM EMPTY BYTES
Later, of course, the temporary storage area is discarded with the sequence LD HL,NPARAM
ADD HL,SP LD SP,HL
;REMOVE NPARAM BYTES FROM STACK
If NPARAM is small, save execution time and memory by replacing these sequences with NPARAM DEC SP or INC SP instructions. Chapter 11 contains examples of simple interrupt service routines.
Interrupt service routines that are based on signals from Z80 peripheral chips (PIOs, SIOs, or CTCs) or that utilize the non-maskable input require special terminating instructions. These special instructions restore the program counter from the top of the stack just like the normal RET. The RETI (return from interrupt) instruction also signals the peripheral chips that the service routine has been completed, thus unblock-ing lower priority interrupts. The RETN (return from non-maskable interrupt) instruction also restores the interrupt enable logic, thus reenabling interrupts if (and only if) they were enabled when the non-maskable interrupt occurred.
CHAPTER 1· GENERAL PROGRAMMING METHODS