Passive Fully Dierential ADC Conversion

The implant's ADC is fully dierential from input to output, and its charge redistribu-tion routine is based on the design from [18]. One aspect of this capacitance to digital conversion system which can be exploited is the fact that the output voltage of the nal pressure to analog voltage conversion is simply the product of the stimulation voltage, the sensor transfer function, and the OTA closed loop gain.

V_out=V_stim

Cs

C_s+ 2C₀

A_cl,

Because the pressure to analog conversion output is a ratiometric conversion from the stimulation voltage, there is no need to generate an accurate reference voltage generator for the ADC conversion. Instead, the best reference for the ADC conversion is the actual stimulation voltage which was used to generate the pressure sample.

During switch phase S1, the ADC samples the CDC conversion result from the OTA onto the top and bottom rails, and the reference potential gets sampled onto the ADC charge redistribution capacitor array at V_REF±. During phase S0, the ADC is electrically disconnected from the rest of the CDC system, and the ADC conversion takes place entirely during CDC switch phase S0. There are no timing conicts between the CDC and ADC during phase S0 because the CDC is running at 4 kHz which means it remains in phase S0 for 125µs, and the 10 bit ADC clock is running at 500 kHz which means it only needs about 20µs to do a complete conversion. As the conversion progresses, each successive ADC capacitor either adds or subtracts charge from the ADC rail potentials until the nal dierential voltage across the top and bottom rail is zero.

6.3.1 The Charge Redistribution Block

The charge redistribution block of the ADC, shown in Figure 6.9a, uses a system of switches to control the charge redistribution of the ADC binary weighted capacitor array as the conversion progresses. Fig.6.9bshows how during the S1 switch phase, the capacitance to analog signal conversion output from the OTA is sampled onto the ADC sample and hold (S/H) capacitor V_RAIL±, and how the stimulation voltage is applied directly from the capacitor bridge to the ADC capacitor array at nodesV_REF±. When V_up, V_dwn, and rst are all open, the ADC capacitor is essentially a oating packet of

S/H

Figure 6.8: The SAR charge redistribution switching array showing the charge redistri-bution block with LSB charge sharing structures [18].

chargeQ=CV_REF± waiting to be added to or subtracted from the charge on the32C S/H capacitor. Figure 6.9: The ADC capacitor charge redistribution block.

a) The generic charge redistribution block.

b) The MSB stage charge redistribution block.

Each block of the ADC charge redistribution array in Fig. 6.8operates as follows:

• During switch phase S1, the CDC conversion result is sampled onto the S/H capacitor, rst is closed sampling the reference onto the ADC capacitor, and V_up andV_dwn are open.

• Next, during switch phase S0, the phase where the rest of the CDC system is resetting itself, S1 and rst are opened, and the ADC conversion commences.

The comparator determines the polarity across _RAIL , and closes stage 9's either V_up or V_dwn switches to add or subtract charge from the S/H capacitor.

• The total rail capacitance is now

C_RAIL = 48C, the total charge is

Q_RAIL =C(32V_in±16V_REF), and the voltage across the rails is

V_RAIL±= Q_RAIL

C_RAIL = 32V_in±16V_REF

48 .

• The comparator makes a decision for the V_RAIL± polarity and switches stage 8 accordingly. After the stage 8 charge redistribution, the voltage across the rails is

V_RAIL±= Q_RAIL

C_RAIL = 32V_in±16V_REF±8V_REF

56 .

• The process is repeated through the rest of the ADC capacitors in successive order untilV_RAIL±= 0 (Fig. 6.10).

Figure 6.10 shows the post layout simulation results of an ADC conversion. As the ADC conversion progresses, the ADC rails V_VRAIL+ and V_VRAIL- are step by step brought closer to each other as their dierential voltage is steadily reduced to zero.

6.3.2 ADC Capacitor Array LSB Charge Sharing

Charge sharing among the 5 LSBs of the ADC capacitor array has been implemented for a couple of dierent reasons. It was stated earlier that using charge sharing among the 4 LSBs helps to improve the INL and DNL performance by reducing the amount of accumulated random error. A larger LSB capacitor is desirable because according to [21] (6.1), the random mismatch attributable to the device area gets smaller as the area increases. There is another reason to try to reduce the MSB/LSB size ratio.

The standard design of an N-bit SAR ADC calls for an MSB/LSB ratio of 2⁹/2⁰ = 512[11]. Even with a 20fF LSB, which would have horrible random mismatch properties (Fig.6.6b), the MSB would be greater than 10pF which is more than twice the required

0 1 2 3

VoltageV

5 6 7 8

0.3 0.4 0.5 0.6 0.8 0.7

4

time sμ

V RAIL-V^RAIL+

Figure 6.10: Spectre post layout simulation results from a single ADC conversion. With each step of the ADC conversion, the dierential voltage gets closer to having 0VDC dierential voltage across the outputs.

capacitance necessary for the OTA amplier to meet its noise requirements which would require more than twice as much power per CDC channel.

The 5 LSB capacitors (stages 5 through 1) plus 1 dummy capacitor (stage 0) are equal in size, and charge sharing is performed between the 4 LSBs and the dummy capacitor as follows [18]

1. During rst, the stage 9 through stage 4 ADC capacitors are reset to the reference voltage, and the stage 3 through stage 0 ADC capacitors are cleared of any stored charge.

2. After rst is released, stage 5 and stage 4 each have Q = CV_ref charge stored on their plates.

3. As the comparator is clocking the stage 9 decision, Share3 is closed, and the Stage 4 and Stage 3 capacitors are shorted together giving each capacitorCV_ref/2 of charge.

4. On the next comparator decision, Share3 is opened, leavingCV_ref/2 of charge on stage 4 and stage 3, and share2 is closed.

5. With the stage 3 and stage 2 ADC caps shorted together, theCV_ref/2charge from stage 3 is evenly divided between stage 3 and stage 2 intoCV_ref/4.

6. This process is repeated through to stage 0 resulting in a binary weighting of charge across the entire capacitor array, while maintaining a more easily achieved 32x ratio between the MSB S/H and LSB capacitor.

Comparator

REF-Figure 6.11: The charge sharing blocks of the ADC Charge redistribution switching array.